| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision |
| resources:alliances:xilinx [25 Sep 2014 06:02] – adding CN0349, CN0354, CN0355 Brandon Bushey | resources:alliances:xilinx [04 Dec 2014 14:25] – [FMC-SDP Interposer] Andrei Cozma |
|---|
| | [[adi>EVAL-AD7091SDZ]] | {{/resources/fpga/xilinx/interposer/ad7091_kc705.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7091|Analog Devices]]\\ \\ The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface. | [[adi>AD7091]] | | | [[adi>EVAL-AD7091SDZ]] | {{/resources/fpga/xilinx/interposer/ad7091_kc705.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7091|Analog Devices]]\\ \\ The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface. | [[adi>AD7091]] | |
| | [[adi>EVAL-AD7091RSDZ]] | {{/resources/fpga/xilinx/interposer/ad7091r_kc705.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7091R|Analog Devices]]\\ \\ The [[adi>AD7091R]] is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | [[adi>AD7091R]] | | | [[adi>EVAL-AD7091RSDZ]] | {{/resources/fpga/xilinx/interposer/ad7091r_kc705.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7091R|Analog Devices]]\\ \\ The [[adi>AD7091R]] is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | [[adi>AD7091R]] | |
| | | [[adi>EVAL-AD7175-2SDZ]] | {{/resources/fpga/xilinx/interposer/ad7176_2.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7176_2|Analog Devices]]\\ \\ The [[adi>AD7175-2]] is a low noise, fast settling, multiplexed, 2-/4- channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 μs) for fully settled data. The output data rates range from 5 SPS to 250 kSPS. The AD7175-2 integrates key analog and digital signal condition-ing blocks to allow users to configure an individual setup for each analog input channel in use. Each feature can be user selected on a per channel basis. Integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. The precision 2.5 V low drift (2 ppm/°C) band gap internal reference (with output reference buffer) adds embedded functionality to reduce external component count. The digital filter allows simultaneous 50 Hz/60 Hz rejection at 27.27 SPS output data rate. The user can switch between different filter options according to the demands of each channel in the application. The ADC automatically switches through each selected channel. Further digital processing functions include offset and gain calibration registers, configurable on a per channel basis. | [[adi>AD7175-2]] | |
| | [[adi>EVAL-AD7176-2SDZ]] | {{/resources/fpga/xilinx/interposer/ad7176_2.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7176_2|Analog Devices]]\\ \\ The [[adi>AD7176-2]] is a fast settling, highly accurate, high resolution, multiplexed S-? analog-to-digital converter (ADC) for low band-width input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer. An integrated precision, 2.5 V, low drift (2 ppm/°C), band gap internal reference (with an output reference buffer) adds functionality and reduces the external component count. The maximum channel scan data rate is 50 kSPS (with a settling time of 20 µs), resulting in fully settled data of 17 noise free bits. User-selectable output data rates range from 5 SPS to 250 kSPS. The resolution increases at lower speeds. The AD7176-2 offers three key digital filters. The fast settling filter maximizes the channel scan rate. The Sinc3 filter maximizes the resolution for single-channel, low speed applications. For 50 Hz and 60 Hz environments, the AD7176-2 specific filter minimizes the settling times or maximizes the rejection of the line frequency. These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-tion with a 27 SPS output data rate (with a settling time of 36 ms). | [[adi>AD7176-2]] | | | [[adi>EVAL-AD7176-2SDZ]] | {{/resources/fpga/xilinx/interposer/ad7176_2.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7176_2|Analog Devices]]\\ \\ The [[adi>AD7176-2]] is a fast settling, highly accurate, high resolution, multiplexed S-? analog-to-digital converter (ADC) for low band-width input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer. An integrated precision, 2.5 V, low drift (2 ppm/°C), band gap internal reference (with an output reference buffer) adds functionality and reduces the external component count. The maximum channel scan data rate is 50 kSPS (with a settling time of 20 µs), resulting in fully settled data of 17 noise free bits. User-selectable output data rates range from 5 SPS to 250 kSPS. The resolution increases at lower speeds. The AD7176-2 offers three key digital filters. The fast settling filter maximizes the channel scan rate. The Sinc3 filter maximizes the resolution for single-channel, low speed applications. For 50 Hz and 60 Hz environments, the AD7176-2 specific filter minimizes the settling times or maximizes the rejection of the line frequency. These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-tion with a 27 SPS output data rate (with a settling time of 36 ms). | [[adi>AD7176-2]] | |
| | [[adi>EVAL-AD7291SDZ]] | {{/resources/fpga/xilinx/interposer/ad7291.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7291|Analog Devices]]\\ \\ The AD7291 is a 12-bit, low power, 8-channel, successive approximation analog-to-digital converter (ADC) with an internal temperature sensor. | [[adi>AD7291]] | | | [[adi>EVAL-AD7291SDZ]] | {{/resources/fpga/xilinx/interposer/ad7291.jpg?150 }} **Reference Design:** [[resources/fpga/xilinx/interposer/ad7291|Analog Devices]]\\ \\ The AD7291 is a 12-bit, low power, 8-channel, successive approximation analog-to-digital converter (ADC) with an internal temperature sensor. | [[adi>AD7291]] | |
