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| resources:alliances:altera [10 May 2013 11:15] – [CED1Z] Added ADAS3023 data acquisition system Adrian Costina | resources:alliances:altera [12 Jun 2013 14:23] – Change the page link for AD7091 Istvan Csomortani |
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| ^ Part Number / Purchase ^ Description ^ ADI Parts ^ | ^ Part Number / Purchase ^ Description ^ ADI Parts ^ |
| ^ ^ Analog to Digital Converters ^ ^ | ^ ^ Analog to Digital Converters ^ ^ |
| | [[adi>EVAL-AD7091SDZ]] | {{/resources/fpga/altera/bemicro/ad7091r_bemicro.jpg?150 }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7091R|ADI Reference Design]] \\ \\ The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface. | [[adi>AD7091]] | | | [[adi>EVAL-AD7091SDZ]] | {{/resources/fpga/altera/bemicro/ad7091_bemicro.jpg?150 }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7091|ADI Reference Design]] \\ \\ The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 μA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The AD7091 operates from a single 2.09 V to 5.25 V power supply. The AD7091 also features an on-chip conversion clock and a high speed serial interface. | [[adi>AD7091]] | |
| | [[adi>EVAL-AD7091RSDZ]] | {{/resources/fpga/altera/bemicro/ad7091r_bemicro.jpg?150 }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7091R|ADI Reference Design]] \\ \\ The AD7091R is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | [[adi>AD7091R]] | | | [[adi>EVAL-AD7091RSDZ]] | {{/resources/fpga/altera/bemicro/ad7091r_bemicro.jpg?150 }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7091R|ADI Reference Design]] \\ \\ The AD7091R is a 12-bit successive approximation analog-to-digital converter (ADC) that offers ultralow power consumption (typically 349 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). Operating from a single 2.7 V to 5.25 V power supply, the part contains a wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 7 MHz. The AD7091R also features an on-chip conversion clock, accurate reference, and high speed serial interface. | [[adi>AD7091R]] | |
| | [[adi>EVAL-AD7176-2SDZ]] | {{/resources/fpga/altera/bemicro/ad7176_2_bemicro.jpg?150 }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7176_2|ADI Reference Design]] \\ \\ The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed S-? analog-to-digital converter (ADC) for low band-width input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer. An integrated precision, 2.5 V, low drift (2 ppm/°C), band gap internal reference (with an output reference buffer) adds functionality and reduces the external component count. The maximum channel scan data rate is 50 kSPS (with a settling time of 20 µs), resulting in fully settled data of 17 noise free bits. User-selectable output data rates range from 5 SPS to 250 kSPS. The resolution increases at lower speeds. The AD7176-2 offers three key digital filters. The fast settling filter maximizes the channel scan rate. The Sinc3 filter maximizes the resolution for single-channel, low speed applications. For 50 Hz and 60 Hz environments, the AD7176-2 specific filter minimizes the settling times or maximizes the rejection of the line frequency. These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-tion with a 27 SPS output data rate (with a settling time of 36 ms). | [[adi>AD7176-2]] | | | [[adi>EVAL-AD7176-2SDZ]] | {{/resources/fpga/altera/bemicro/ad7176_2_bemicro.jpg?150 }} **Reference Design:** [[/resources/fpga/altera/bemicro/ad7176_2|ADI Reference Design]] \\ \\ The AD7176-2 is a fast settling, highly accurate, high resolution, multiplexed S-? analog-to-digital converter (ADC) for low band-width input signals. Its inputs can be configured as two fully differential or four pseudo differential inputs via the integrated crosspoint multiplexer. An integrated precision, 2.5 V, low drift (2 ppm/°C), band gap internal reference (with an output reference buffer) adds functionality and reduces the external component count. The maximum channel scan data rate is 50 kSPS (with a settling time of 20 µs), resulting in fully settled data of 17 noise free bits. User-selectable output data rates range from 5 SPS to 250 kSPS. The resolution increases at lower speeds. The AD7176-2 offers three key digital filters. The fast settling filter maximizes the channel scan rate. The Sinc3 filter maximizes the resolution for single-channel, low speed applications. For 50 Hz and 60 Hz environments, the AD7176-2 specific filter minimizes the settling times or maximizes the rejection of the line frequency. These enhanced filters enable simultaneous 50 Hz and 60 Hz rejec-tion with a 27 SPS output data rate (with a settling time of 36 ms). | [[adi>AD7176-2]] | |
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| ^ Part Number / Purchase ^ Description ^ ADI Parts ^ | ^ Part Number / Purchase ^ Description ^ ADI Parts ^ |
| | | [[adi>EVAL-AD7262EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7262.png?150 }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7262|ADI Reference Design]] \\ \\ The AD7262 are dual, 12-bit, high speed, low power, successive approximation ADCs that operate from a single 5 V power supply. The AD7262 features throughput rates of up to 1 MSPS per on-chip ADC. Two complete ADC functions allow simultaneous sampling and conversion of two channels. Each ADC is preceded by a true differential analog input with a PGA. There are 14 gain settings available: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.| [[adi>AD7262]] | |
| | [[adi>EVAL-AD7400EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7400a.png?150 }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7400a|ADI Reference Design]] \\ \\ The AD7400 is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7400]] | | | [[adi>EVAL-AD7400EDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7400a.png?150 }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7400a|ADI Reference Design]] \\ \\ The AD7400 is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400 operates from a 5 V power supply and accepts a differential input signal of ±200 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7400]] | |
| | [[adi>EVAL-AD7400AEDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7400a.png?150 }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7400a|ADI Reference Design]] \\ \\ The AD7400A is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400A operates from a 5 V power supply and accepts a differential input signal of ±250 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7400A]] | | | [[adi>EVAL-AD7400AEDZ]] | {{/resources/fpga/altera/ced1z/ced1z_ad7400a.png?150 }} **Reference Design:** [[/resources/fpga/altera/ced1z/ad7400a|ADI Reference Design]] \\ \\ The AD7400A is a second-order, sigma-delta modulator that converts an analog input signal into a high speed, 1-bit data stream with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7400A operates from a 5 V power supply and accepts a differential input signal of ±250 mV (±320 mV full scale). The analog input is sampled continuously by the analog modulator, eliminating the need for external sample-and-hold circuitry. The input information is contained in the output stream as a density of ones with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter. The serial I/O can use a 5 V or a 3 V supply (VDD2). | [[adi>AD7400A]] | |
