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resources:fpga:xilinx:kc705:adv7511 [18 Nov 2019 15:56] – Stanca-Florina Pop | resources:fpga:xilinx:kc705:adv7511 [08 Feb 2021 13:21] (current) – Change broken link Iulia Moldovan | ||
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===== Introduction ===== | ===== Introduction ===== | ||
- | The [[adi> | + | The [[adi> |
===== Supported Carriers ===== | ===== Supported Carriers ===== | ||
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* [[xilinx> | * [[xilinx> | ||
* [[xilinx> | * [[xilinx> | ||
- | * [[http://zedboard.com/ | + | * [[xilinx> |
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==== Running Demo (SDK) Program ==== | ==== Running Demo (SDK) Program ==== | ||
- | To begin, connect an HDMI cable between the board HDMI out and the HDMI monitor. After the hardware setup, turn the power on to the board. | + | The following steps will get your system up and running. |
- | Run the **//evaluate.bat//** script. This script uses XMD to program the FPGA with the HDL Reference Design | + | - To begin, connect an HDMI cable between |
+ | - Download the [[adi> | ||
+ | - Build the HDL project according | ||
+ | - Choose the carrier board in the software by uncommenting the appropriate define in the **src/ | ||
+ | - Build the software project according to the [[https:// | ||
- | **Note: | + | < |
If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. | If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. | ||
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{{resources: | {{resources: | ||
- | The reference design consists of two independent | + | The reference design consists of two independent |
The video part consists of an AXI DMAC interface and the ADV7511 video interface. The ADV7511 interface consists of a 16bit YCbCr 422 with separate synchroinzation signals. The DMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable. | The video part consists of an AXI DMAC interface and the ADV7511 video interface. The ADV7511 interface consists of a 16bit YCbCr 422 with separate synchroinzation signals. The DMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable. | ||
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The project contains 2 components: the Reference Design files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the **Downloads** section. | The project contains 2 components: the Reference Design files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the **Downloads** section. | ||
- | ==== Software | + | ==== Serial |
- | + | ||
- | Example for a ZC702 board: | + | |
- | * After [[http:// | + | |
- | * Open the Xilinx SDK for Vivado. When the SDK starts it asks to provide a folder where to store the workspace. Any folder can be provided. | + | |
- | * Go to // | + | |
- | {{ : | + | |
- | * Use a new hardware platform, so choose //**New**// in //**Target Hardware**// | + | |
- | {{ : | + | |
- | * At the **Target Hardware Specification** section browse the location of the hardware description file. This file's extension should be **.xml** or **.hdf**, and is located in the directory of the hdl design. **Note:** If the file does not exist, probably you forgot to make an **Export hardware** (in Vivado **File** -> **Export** -> **Export Hardware...**) | + | |
- | {{ : | + | |
- | * Then give a name to the project and click // | + | |
- | {{ : | + | |
- | * In the next window choose //**Empty Application**// | + | |
- | {{ : | + | |
- | * Now the project without source code looks like this | + | |
- | {{ : | + | |
- | * Then the no-OS software for the used FPGA board must be added from Github. Also the library must be added (ZC library for a Zynq based platform(except ZED), ZED library for a ZED platform or Microblaze library for AC701, | + | |
- | {{ : | + | |
- | * Afterwards click right on project name and go to // | + | |
- | {{ : | + | |
- | * In the window that appears, go to // | + | |
- | {{ : | + | |
- | * In the same window, go to // | + | |
- | {{ : | + | |
- | * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the Console window will display the result of the build. If the build is not done automatically select the // | + | |
- | {{ : | + | |
- | * At this point the software project setup is complete, the FPGA can be programmed and the software can be downloaded into the system. You can program the FPGA by going to //**Xilinx Tools**// | + | |
- | {{ : | + | |
- | * Then choose this bitstream and press // | + | |
- | {{ : | + | |
- | * This window will appear next. | + | |
- | {{ : | + | |
- | * Afterwards a //Run Configuration// | + | |
- | {{ : | + | |
* The no-OS drivers source code does the following actions: | * The no-OS drivers source code does the following actions: | ||
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* This is what is transmitted through UART: | * This is what is transmitted through UART: | ||
{{ : | {{ : | ||
- | * The output of the example program can be viewed in the SDK console by enabling the //Connect STDIO Console// option and setting the baud rate of the UART port to 115200. | ||
- | {{ : | ||
As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer' | As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer' | ||
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The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices Github.\\ | The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices Github.\\ | ||
\\ | \\ | ||
- | |||
- | **Evaluation Scripts:** | ||
- | <WRAP round download 80%> | ||
- | * **AC701 Evaluation Script: ** [[https:// | ||
- | * **KC705 Evaluation Script: ** [[https:// | ||
- | * **VC707 Evaluation Script: ** [[https:// | ||
- | * **ZC702 Evaluation Script: ** [[https:// | ||
- | * **ZC706 Evaluation Script: ** [[https:// | ||
- | * **Zed Evaluation Script: ** [[https:// | ||
- | </ | ||
**HDL Reference Designs:** | **HDL Reference Designs:** | ||
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**no-OS Software:** | **no-OS Software:** | ||
<WRAP round download 80%> | <WRAP round download 80%> | ||
- | * **ADV7511 | + | * **ADV7511 |
- | * **ADV7511 AC701 Reference Design: ** https:// | + | |
- | * **ADV7511 KC705 Reference Design: ** https:// | + | |
- | * **ADV7511 VC707 Reference Design: ** https:// | + | |
- | * **ADV7511 ZC Library: ** https:// | + | |
- | * **ADV7511 ZC702 Reference Design: ** https:// | + | |
- | * **ADV7511 ZC706 Reference Design: ** https:// | + | |
- | * **ADV7511 ZedBoard Library: ** https:// | + | |
- | * **ADV7511 ZedBoard Reference Design: ** https:// | + | |
</ | </ | ||
<WRAP round help 80%> | <WRAP round help 80%> | ||
- | * Questions? [[https://ez.analog.com/ | + | * Questions? [[ez>community/ |
</ | </ | ||