The ADV7511 is a 225 MHz High-Definition Multimedia Interface (HDMI®) transmitter. It is part of the Kintex-7 KC705, Virtex-7 VC707, Zynq ZC702 and the Zynq ZED evaluation boards. This reference design provides the video and audio interface between the FPGA and ADV7511 on board. The video uses a 16bit 422 YCbCr interface (except VC707 which uses 36bit 444 RGB interface) and the audio uses a single bit SPDIF interface.
To begin, connect an HDMI cable between the board HDMI out and the HDMI monitor. After the hardware setup, turn the power on to the board.
Run the download.bat script located in the ”SDK/SDK_Workspace/bin” folder provided within the HDL Reference Design. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.
Note: The download.bat script assumes that the Xilinx ISE Design Suite 14.4 is installed at this path: C:/Xilinx/14.4. If the installation path on your computer is different please modify the script accordingly.
If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.
The reference design contains an example of how to:
The reference design consists of two independent pcore modules.
The video part consists of a Xilinx VDMA interface and the ADV7511 video interface. The ADV7511 interface consists of a 16bit YCbCr 422 with separate synchorinzation signals. The VDMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.
The reference design defaults to the 1080p video mode. Users may change the video settings by programming the following registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally.
HSYNC count: is the total horizontal pixel clocks of the video, for 1080p this is 2200.
HSYNC width: is the pulse width in pixel clocks, for 1080p this is 44.
HSYNC DE Minimum: is the number of pixel clocks for the start of active video and is the sum of horizontal sync width and back porch, for 1080p this is 192 (44 + 148).
HSYNC DE Maximum: is the number of pixel clocks for the end of active video and is the sum of horizontal sync width, back porch and the active video count, for 1080p this is 2112 (44 + 148 + 1920).
VSYNC count: is the total vertical pixel clocks of the video, for 1080p this is 1125.
VSYNC width: is the pulse width in pixel clocks, for 1080p this is 5.
VSYNC DE Minimum: is the number of pixel clocks for the start of active video and is the sum of vertical sync width and back porch, for 1080p this is 41 (5 + 36).
VSYNC DE Maximum: is the number of pixel clocks for the end of active video and is the sum of vertical sync width, back porch and the active video count, for 1080p this is 1121 (5 + 36 + 1080).
Note that the pixel frequency for 1080p is 148.5MHz.
The reference design reads 24bits of RGB data from DDR and performs color space conversion (RGB to YCbCr) and down sampling (444 to 422). If bypassed, the lower 16bits of DDR data is passed to the HDMI interface as it is.
A color pattern register provides a quick check of any RGB values on the monitor. If enabled, the register data is used as the pixel data for the entire frame.
The audio part consists of a Xilinx DMA interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz.
Please refer to the regmap.txt file inside the pcores.
|0x00||23:20||0||mode||Sample format 0 to 8 (0-16bit, 8-24bit).|
|15:8||0||ratio||Clock divider for the transmit frequency = bus_clock/(1+ratio).|
|1||0||txdata||Transmit data buffer enable (0x1) or disable (0x0).|
|0||0||txenable||Transmitter enable (0x1) or disable (0x0).|
|0x01||7:6||0||frequency||Sample frequency 0(44.1KHz), 1(48KHz), 2(32KHz) or 3(sample rate converter) (RO).|
|3||0||gstat||Generation status original/commercially pre-recorded data (0x1) or none (0x0) (RO).|
|2||0||pre-emphasis||Pre-emphasis 50/15s (0x1) or none (0x0) (RO).|
|1||0||copy||Copy permitted (0x1) or inhibited (0x0) (RO).|
|0||0||audio||Data format is non-audio (0x1) or audio (0x0) (RO).|
|1. For AXI-Lite byte addresses, multiply by 4.|
The Software Reference Design uses the ADV7511 Transmitter Library which is a collection of APIs that provide a consistent interface to ADV7511. The library is a software layer that sits between the application and the TX hardware and it is intended to serve two purposes:
The documentation for the library's API can be accessed here: ADV7511 Transmitter API Documentation
The project contains 2 components: the Reference Design files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the Downloads section.
The HDL Reference Design for each supported Xilinx FPGA board contains a folder called SDK_Workspace which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA. These are the steps that need to be followed to recreate the software project:
The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.
The software project contains 2 components: the Reference Design files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links below.
HDL Reference Designs:
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
|license.txt||ADI license & copyright information.|
|system.xmp||XMP file (use this file to build the reference design).|
|data/||UCF file and/or DDR MIG project files.|
|docs/||Documentation files (Please note that this wiki page is the documentation for the reference design).|
|sw/||Software (Xilinx SDK) & bit file(s).|
|cf_lib/edk/pcores/||Reference design core file(s) (Xilinx EDK).|