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This version is outdated by a newer approved version.This version (28 Sep 2012 15:00) was approved by Adrian Costina.The Previously approved version (28 May 2012 15:55) is available.
This version is outdated by a newer approved version.This version (28 Sep 2012 15:00) was approved by Adrian Costina.The Previously approved version (28 May 2012 15:55) is available.This is an old revision of the document!
Table of Contents
CN0178 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design
Supported Devices
Evaluation Boards
Overview
This document presents the steps to setup an environment for using the EVAL-CN0178-SDPZ evaluation board together with the Xilinx KC705 FPGA board, the Xilinx Embedded Development Kit (EDK) and the Micrium µC-Probe run-time monitoring tool. Below is presented a picture of the EVAL-CN0178-SDPZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
- 1. A controller board like the SDP-B ( EVAL-SDP-CS1Z)
- 2. The component SDP compatible product evaluation board
- 3. Corresponding PC software ( shipped with the product evaluation board)
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-CN0178-SDPZ Evaluation Board.
The CN0178 circuit uses the ADL5902 TruPwr™ detector to measure the rms signal strength of RF signals with varying crest factors (peak-to-average ratio) over a dynamic range of approximately 65 dB and operates at frequencies from 50 MHz up to 9 GHz.
The measurement result is provided as serial data at the output of a 12-bit ADC (AD7466).
The ADL5902 is a true rms responding power detector that has a 65 dB measurement range when driven with a single-ended 50 O source. This feature makes the ADL5902 frequency versatile by eliminating the need for a balun or any other form of external input tuning for operation up to 9 GHz. The ADL5902 provides a solution in a variety of high frequency systems requiring an accurate measurement of signal power. Requiring only a single supply of 5 V and a few capacitors, it is easy to use and capable of being driven single-ended or with a balun for differential input drive. The ADL5902 can operate from 50 MHz to 9 GHz and can accept inputs from -62 dBm to at least +3 dBm with large crest factors, such as GSM, CDMA, W-CDMA, TD-SCDMA, WiMAX, and LTE modulated signals.
The AD7466 is 12-bit, high speed, low power, successive approximation analog-to-digital converter (ADC). The part operates from a single 1.6 V to 3.6 V power supply and feature throughput rates up to 200 kSPS with low power dissipation. The part contains a low noise, wide bandwidth track-and-hold amplifier, which can handle input frequencies in excess of 3 MHz.
The EVAL-CN0178-SDP board contains the circuit to be evaluated, as described in this note. To power the EVAL-CN0178C-SDP evaluation board supply +6V between the +6 V and GND inputs.
More information
- CN0178 Info - circuit note information
- ADL5902 Product Info - pricing, samples, datasheet
- AD7466 Product Info - pricing, samples, datasheet
Getting Started
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.
Required Hardware
- FMC-SDP adapter board
- EVAL-CN0178-SDPZ evaluation board
Required Software
- Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
- uC-Probe run-time monitoring tool
Downloads
The following table presents a short description the reference design archive contents.
| Folder | Description |
|---|---|
| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. |
| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. |
| Software | Contains the source files of the software project that will be run by the Microblaze processor. |
| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. |
Run the Demonstration Project
Hardware Setup
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
- Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
- Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
- Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).
- Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
- Power the ADI evaluation board.
At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design.
Configure uC-Probe
Launch uC-Probe from the Start → All Programs → Micrium → uC-Probe.
Select uC-Probe options.
- Click on the uC-Probe icon on the top left portion of the screen.
- Click on the Options button to open the dialog box.
Set target board communication protocol as RS-232
- Click on the Communication tab icon on the top left portion of the dialog box
- Select the RS-232 option.
Setup RS-232 communication settings
- Select the RS-232 option from the Communication tab.
- Select the COM port to which the KC705 board is connected.
- Set the Baud Rate to 115200 bps.
- Press Apply and OK to exit the options menu.
Load and Run the Demonstration Project
- Click the Open option from the uC-Probe menu and select the .wsp file from the ucProbeInterface folder provided within the reference design files.
- Before opening the interface uC-Probe will ask for a symbols file that must be associated with the interface. Select the file ucProbeInterface/ADIEvalBoard.elf to be loaded as a symbol file.
- Run the demonstration project by pressing the Play button.
- In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the Stop button and run it again by pressing the Play button.
- After starting the uC-Probe interface wait until the status of the connection with the board displayed on the bottom of the screen is set to Connected. It is possible to use the interface only after the status is changed to Connected and the data transfer speed displayed next to the connection status is different than 0.
Demonstration Project User Interface
The following figure presents the uC-Probe interface that can be used for monitoring and controlling the operation of the EVAL-CN0178-SDPZ evaluation board.
Section A is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the ON/OFF switch. The Activity LED turns green when the communication is active. If the ON/OFF switch is set to ON and the Activity LED is BLACK it means that there is a communication problem with the board.
Section B is used to select the sample size and to initiate a data acquisition. The value of the “Sample Size” slider controls the number of datapoints to collect. From these datapoints is calculated an average value, which is stored in ADC Code Column (the position is auto incremented). Acquire Data button initiates a data acquisition.
Section C is used to store the calibration data and to display the calculated information. The calibration is performed by applying four known signal levels to the ADL5902 and measuring the corresponding output codes from the ADC. The calibration points chosen should be within the linear operating range of the device. In this example, calibration points at 10 dBm, 0 dBm, -10 dBm, and -20 dBm were used.
User has to add manually ADC Code and Input Power for each signal, in the Calibration Data section. Frequency and temperature are optional. Slope and Intercept are calculated by the interface.
The SLOPE and INTERCEPT calibration coefficients are calculated using the equations:
- SLOPE1 = ( CODE _1 – CODE_2) / (PIN_1 - PIN_2)
- INTERCEPT1 = CODE_1 / (SLOPE_ADC × PIN_1)
This calculation is then repeated using CODE_2/CODE_3 and CODE_3/CODE_4 to calculate SLOPE2/INTERCEPT2 and SLOPE3/INTERCEPT3, respectively.
When the circuit is in operation in the field, these calibration coefficients are used to calculate an unknown input power level, PIN, using the equation:
- PIN = (CODE / SLOPE) + INTERCEPT
In order to retrieve the appropriate SLOPE and INTERCEPT calibration coefficients during circuit operation, the observed CODE from the ADC must be compared to CODE_1, CODE_2, CODE_3, and CODE_4. For example if the CODE from the ADC is between CODE_1 and CODE_2, then the SLOPE1 and INTERCEPT1 should be used.
The interface chooses the slope and intercept for each ADC code and calculates the Power. For the error to be calculated, it is necessary to add manually the Input Power. Frequency and temperature are optional.
Troubleshooting
In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues:
- Check that the evaluation board is powered as instructed in the board's user guide.
- In uC-Probe refresh the symbols file by right-clicking on the System Browser window and selecting Refresh Symbols.
- If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.
More information
- Example questions:
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resources/fpga/xilinx/interposer/cn0178.1348837215.txt.gz · Last modified: 28 Sep 2012 15:00 by Adrian Costina