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resources:fpga:xilinx:interposer:ad5694r [28 Sep 2012 11:22] – Added common section for describing the evaluation setup and System Demonstration Platform Adrian Costina | resources:fpga:xilinx:interposer:ad5694r [09 Jan 2021 00:48] (current) – user interwiki links Robin Getz | ||
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====== Overview ====== | ====== Overview ====== | ||
- | This document presents the steps to setup an environment for using the **[[adi> | + | This document presents the steps to setup an environment for using the **[[adi> |
{{ : | {{ : | ||
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* [[adi> | * [[adi> | ||
* EVAL-AD5694RSDZ evaluation board user guide | * EVAL-AD5694RSDZ evaluation board user guide | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
- | * [[http:// | + | |
====== Getting Started ====== | ====== Getting Started ====== | ||
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===== Required Hardware ===== | ===== Required Hardware ===== | ||
- | * [[http://www.xilinx.com/products/ | + | * [[xilinx>products/ |
* FMC-SDP adapter board | * FMC-SDP adapter board | ||
* **EVAL-AD5694R** evaluation board | * **EVAL-AD5694R** evaluation board | ||
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===== Required Software ===== | ===== Required Software ===== | ||
- | * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). | + | * Xilinx ISE 14.6. |
- | * [[http://micrium.com/ | + | * UART Terminal (Termite/Tera Term/Hyperterminal), |
+ | * The EVAL-AD5694R reference project for Xilinx KC705 FPGA. | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | + | <WRAP round download 80%> | |
- | * {{:resources: | + | \\ |
- | + | * **AD5694R Driver:** https://github.com/ | |
- | The following table presents a short description the reference design archive contents. | + | * **AD5694R Commands:** https:// |
- | + | | |
- | ^ **Folder** ^ **Description** ^ | + | * **EDK KC705 Reference |
- | | Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation. | | + | \\ |
- | | Microblaze | Contains the EDK project for the Microblaze softcore that will be implemented in the KC705 FPGA. | | + | </ |
- | | Software | Contains the source files of the software | + | |
- | | uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microbalze memory. | | + | |
====== Run the Demonstration Project ====== | ====== Run the Demonstration Project ====== | ||
- | ===== Hardware | + | ===== Hardware |
- | <note important> | + | <WRAP round important |
+ | \\ | ||
+ | Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. | ||
+ | </WRAP> | ||
* Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. | * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. | ||
* Connect the JTAG and UART cables to the KC705 and power up the FPGA board. | * Connect the JTAG and UART cables to the KC705 and power up the FPGA board. | ||
- | * Start IMPACT, and double click “// | ||
- | {{ : | ||
- | * Program the KC705 FPGA using the "// | ||
- | * Power the ADI evaluation board. | ||
- | |||
- | At this point everything is set up and it is possible to start the evaluation of the ADI hardware through the controls in the uC-Probe application provided in the reference design. | ||
- | |||
- | ===== Configure uC-Probe ===== | ||
- | |||
- | Launch **uC-Probe** from the **//Start -> All Programs -> Micrium -> uC-Probe// | ||
- | |||
- | Select **uC-Probe** options. | ||
- | * Click on the **uC-Probe** icon on the top left portion of the screen. | ||
- | * Click on the **// | ||
- | |||
- | {{ : | ||
- | |||
- | Set target board communication protocol as **// | ||
- | * Click on the **// | ||
- | * Select the **// | ||
- | |||
- | {{ : | ||
- | |||
- | Setup **// | ||
- | * Select the **// | ||
- | * Select the COM port to which the KC705 board is connected. | ||
- | * Set the Baud Rate to 115200 bps. | ||
- | |||
- | {{ : | ||
- | |||
- | * Press **// | ||
- | |||
- | ===== Load and Run the Demonstration Project ===== | ||
- | |||
- | * Click the **// | ||
- | |||
- | * Before opening the interface **uC-Probe** will ask for a symbols file that must be associated with the interface. Select the file **// | ||
- | |||
- | * Run the demonstration project by pressing the **// | ||
- | |||
- | {{ : | ||
- | |||
- | <note tip>In some cases it is possible that the uC-Probe interface will not respond to the commands the first time it is ran. In this situation just stop the interface by pressing the **// | ||
- | |||
- | ===== Demonstration Project User Interface ===== | ||
- | |||
- | The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD5694RSDZ** evaluation board. | ||
- | |||
- | {{ : | ||
- | |||
- | **Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the //ON/OFF// switch. The // | ||
- | |||
- | **Section B** is used to select the //Command// to be sent to the DAC. The definition of each command is available in Table 7 of the part's datasheet. | ||
- | |||
- | **Section C** is used to select the //Address// of the registers to be affected by the command, if the command is 1, 2 or 3. If the selected command is 5, the //Address// buttons will be used to program the //LDAK MASK REGISTER// for the corresponding DAC. For the other commands, they are ignored. | ||
- | |||
- | **Section D** is used to program the value to be written to the DAC registers. | ||
- | |||
- | **Section E** is used to send the selected command to the DAC. | ||
- | **Section F** is used to configure | + | <WRAP round important 80%> |
+ | \\ | ||
+ | To power on the EVAL-AD5694R evaluation board, you need to apply +6V supply voltage to J3 connector of the board. | ||
+ | </ | ||
- | **Section G** is used to configure | + | ===== Reference Project Overview ===== |
+ | The following commands were implemented in this version of EVAL-AD5694R reference project for Xilinx KC705 FPGA board. | ||
+ | ^ Command ^ Description ^ | ||
+ | | **help?** | Displays all available commands. | | ||
+ | | **reset!** | Activate a power-on reset. | | ||
+ | | **load=** | Loads selected DAC input register with a given value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ value:\\ 0 .. 4095 - value to be written in register. | | ||
+ | | **update=** | Update the selected DAC channel with the input register. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels. | | ||
+ | | **loadAndUpdate=** | Loads and updates the selected DAC with a given value. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ value:\\ 0 .. 4095 - value to be written in register. | | ||
+ | | **pwrMode=** | Set up the Power Mode of a selected channel. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels.\\ power mode:\\ 0 - normal operation.\\ 1 - 1KOhm to GND.\\ 2 - 100KOhms to GND.\\ 3 - three-state. | | ||
+ | | **pwrMode? | ||
+ | | **ldacMask=** | Set up the LDAC mask register. Accepted values:\\ channel:\\ 0 - select channel A.\\ 1 - select channel B.\\ 2 - select channel C.\\ 3 - select channel D.\\ 4 - select all channels.\\ set/reset mask:\\ 0 - reset LDAC mask for the selected channel.\\ 1 - set LDAC mask for the selected channel. | | ||
+ | | **ldacMask? | ||
+ | | **intRef=** | Turns ON or OFF the internal | ||
+ | | **intRef?** | Displays the status of the internal reference. | | ||
+ | | **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. | | ||
+ | | **ldacPin? | ||
- | **Section H** is used to control the Hardware pins of the AD7694R. | ||
- | **Section I** is used to perform a readback of all four registers | + | Commands can be executed using a serial terminal connected |
- | ===== Troubleshooting ===== | + | The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. |
+ | {{ : | ||
- | In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: | + | ===== Software Project Setup ===== |
- | * Check that the evaluation board is powered as instructed in the board' | + | {{page> |
- | * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols// | + | |
- | * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again. | + | |
====== More information ====== | ====== More information ====== | ||
{{page> | {{page> |