This version (02 Mar 2021 16:20) was approved by Laszlo Nagy.The Previously approved version (14 Jan 2021 05:11) is available.
Table of Contents
ADRV9001/ADRV9002 HDL Reference Design
This design allows controlling, receiving and transmitting sample stream from/to an ADRV9001/ADRV9002 device through two independent source synchronous interface. Supports both CMOS and LVDS interface, but not in the same time. The selection of the I/O standard must be done with a parameter during build.
The design supports SDR or DDR modes in CMOS mode with one of four lanes, as in LVDS mode one or two lane mode. This is runtime selectable. The complete list of supported modes can be consulted in the AXI_ADRV9001/AXI_ADRV9002 Interface Core documentation.
Source code
The source files can be accessed at:
Build instructions:
For an LVDS interface the project must be built with the following parameters:
make CMOS_LVDS_N=0For a CMOS interface the project must be built with the following parameters:
make CMOS_LVDS_N=1
Block design
The design has two receive paths and two transmit paths. One of the receive paths (Rx12) has four channels and the other (Rx2) two channels. These can work independently having each two active channels, or just the Rx12 path having four active channels, while Rx2 is disabled. The same applies to the transmit path but in the other direction.
When only the Rx12 path is active with four channels mode the core will take ownership of both source synchronous interfaces. The requirement in this case is that both interfaces run at the same rate.
FMC locations
- ZCU102 - FMC0
DAC Interface
- Has DDS
- Has PRBS generation
ADC Interface
- Has PN checking
- Has data formater
- Has programmable input delay
SW programming
Register map
| Address | IP |
| 0x44A00000 | axi_adrv9001 |
|---|---|
| 0x44A30000 | axi_adrv9001_rx1_dma |
| 0x44A40000 | axi_adrv9001_rx2_dma |
| 0x44A50000 | axi_adrv9001_tx1_dma |
| 0x44A60000 | axi_adrv9001_tx2_dma |
===ZC706 VADJ protection=== For ZC706 after bitfile loading all outputs of FPGA are high Z . * SW should wait until the VADJ is set to 1.8V * Set GPIO[52] to enable the output lines. * Pull out of reset the RX and TX channels (ADC/DAC common REG_RSTN reg RSTN bit)
More Information
Support
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone.
resources/eval/user-guides/adrv9002/reference_hdl.txt · Last modified: 02 Mar 2021 16:18 by Laszlo Nagy