This version is outdated by a newer approved version.
This version (17 Nov 2020 14:29) is a draft.
Approvals: 0/1
This version (17 Nov 2020 14:29) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
AD469X HDL Reference Design
Overview
The AD469X HDL reference design provides all the interfaces that are necessary to interact with the devices on the AD469X eval board.
The design has a SPI Engine instance to control and acquire data from the AD4696 16-bit precisions ADC, providing support to capture continuous samples at maximum sampling rate. Currently the design supports the Zedboard.
Used devices
Supported FPGA carrier
HDL Design Description
The design is built upon ADI's generic HDL reference design framework. In the ADI Reference Designs HDL User Guide can be found an in-depth presentation and instructions about the HDL design framework in general.
The reference design uses the standard SPI Engine Framework to interface the AD4696 ADC in single SDO Mode. The SPI offload module, which can be used to capture continuous data stream at maximum data rate, is triggered by the BUSY signal of the device.
In order to build the HDL design the user has to go through the following steps:
- Confirm that you have the right tools (see Release notes)
- Clone the HDL GitHub repository (see https://wiki.analog.com/resources/fpga/docs/git)
- Build the project (see https://wiki.analog.com/resources/fpga/docs/build)
HDL Downloads
Software sources
resources/eval/user-guides/ad469x.1605619769.txt.gz · Last modified: 17 Nov 2020 14:29 by sergiu arpadi