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resources:eval:ad9684-500ebz [13 Jan 2023 02:35] – [Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2] John Xavier Toledoresources:eval:ad9684-500ebz [13 Jan 2023 02:42] (current) – [Device Setup - Full Bandwidth Mode] John Xavier Toledo
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 ==== Device Setup - Full Bandwidth Mode ==== ==== Device Setup - Full Bandwidth Mode ====
-  - The settings in the ADCBase0 tab must be changed to configure the AD9684. In this example, the AD9684 is set up to use **Full Bandwidth Mode** for 2 ADC channels.  Set the Chip Application Mode in register 0x200 to **Full Bandwidth Mode**.  Set the Chip Decimation Ratio in register 0x201 to **Full Sample Rate**. {{ :resources:eval:ad9684_full_bw_mode.png?800 |}}<WRAP centeralign>//Figure 11. Set Application Mode to Full Bandwidth Mode//</WRAP>+  - The settings in the ADCBase0 tab must be changed to configure the AD9684. In this example, the AD9684 is set up to use **Full Bandwidth Mode** for 2 ADC channels.  Set the Chip Application Mode in register 0x200 to **Full Bandwidth Mode**.  Set the Chip Decimation Ratio in register 0x201 to **Full Sample Rate**. Since the chip is configured to Full Bandwidth mode, the DDC configuration is bypassed and the sampling frequency is decimated by 1. {{ :resources:eval:ad9684_full_bw_mode.png?800 |}}<WRAP centeralign>//Figure 11. Set Application Mode to Full Bandwidth Mode//</WRAP>
  
  
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   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_2ddcrealdec2.png?600 |}}<WRAP centeralign>//Figure 17. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP>   - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_2ddcrealdec2.png?600 |}}<WRAP centeralign>//Figure 17. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP>
   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range.  A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog.   - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range.  A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog.
-  -  To save the FFT plot do the following +  - To save the FFT plot do the following: 
-    - Click on the Float Form button in the FFT window +      - Click on the Float Form button in the FFT window {{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 18. Floating the FFT window//</WRAP> 
-{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 18. Floating the FFT window//</WRAP> +      - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 19. Saving the FFT//</WRAP>
-    - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 19. Saving the FFT//</WRAP>+
 ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ====
     - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC.   In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two.  Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked.  Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 20. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2//</WRAP>     - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC.   In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two.  Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked.  Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 20. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2//</WRAP>
resources/eval/ad9684-500ebz.1673573734.txt.gz · Last modified: 13 Jan 2023 02:35 by John Xavier Toledo

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