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| resources:eval:ad9684-500ebz [13 Jan 2023 02:26] – [Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2] John Xavier Toledo | resources:eval:ad9684-500ebz [13 Jan 2023 02:42] (current) – [Device Setup - Full Bandwidth Mode] John Xavier Toledo |
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| ==== Device Setup - Full Bandwidth Mode ==== | ==== Device Setup - Full Bandwidth Mode ==== |
| - The settings in the ADCBase0 tab must be changed to configure the AD9684. In this example, the AD9684 is set up to use **Full Bandwidth Mode** for 2 ADC channels. Set the Chip Application Mode in register 0x200 to **Full Bandwidth Mode**. Set the Chip Decimation Ratio in register 0x201 to **Full Sample Rate**. {{ :resources:eval:ad9684_full_bw_mode.png?800 |}}<WRAP centeralign>//Figure 11. Set Application Mode to Full Bandwidth Mode//</WRAP> | - The settings in the ADCBase0 tab must be changed to configure the AD9684. In this example, the AD9684 is set up to use **Full Bandwidth Mode** for 2 ADC channels. Set the Chip Application Mode in register 0x200 to **Full Bandwidth Mode**. Set the Chip Decimation Ratio in register 0x201 to **Full Sample Rate**. Since the chip is configured to Full Bandwidth mode, the DDC configuration is bypassed and the sampling frequency is decimated by 1. {{ :resources:eval:ad9684_full_bw_mode.png?800 |}}<WRAP centeralign>//Figure 11. Set Application Mode to Full Bandwidth Mode//</WRAP> |
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| ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== |
| - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 and DDC1 are being used in the AD9684 so this must be selected under the ADC Data Capture Settings. | - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 and DDC1 are being used in the AD9684 so this must be selected under the ADC Data Capture Settings. |
| - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_2ddcrealdec2.png?600 |}}<WRAP centeralign>//Figure 13. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP> | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_2ddcrealdec2.png?600 |}}<WRAP centeralign>//Figure 17. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP> |
| - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. A -1.0 dBFS input signal will show as -1.7 dBFS in the FFT in Visual Analog. |
| - To save the FFT plot do the following | - To save the FFT plot do the following: |
| - Click on the Float Form button in the FFT window | - Click on the Float Form button in the FFT window {{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 18. Floating the FFT window//</WRAP> |
| {{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 14. Floating the FFT window//</WRAP> | - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 19. Saving the FFT//</WRAP> |
| - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:ad9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 15. Saving the FFT//</WRAP> | |
| ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== |
| - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC. In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 16. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2//</WRAP> | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC. In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. Set the Chip Decimation Ratio in register 0x201 to Decimate by 2 Ratio. {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcglobal.png?800 |}}<WRAP centeralign>//Figure 20. Set Application Mode to 1 DDC Complex ZIF Mode Decimate by 2//</WRAP> |
| - The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | - The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. |
| - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcbase1.png?400 |}}<WRAP centeralign>//Figure 17. DDC Settings for Complex ZIF Mode//</WRAP> | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ :resources:eval:AD6674_spi_2adc1ddccomplexdec2_adcbase1.png?400 |}}<WRAP centeralign>//Figure 21. DDC Settings for Complex ZIF Mode//</WRAP> |
| ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== |
| - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 is being used in the AD9684 so this must be selected under the ADC Data Capture Settings.{{ :eval:AD9684_2ddcrealdec2_datacapturesettings.png?400 |}}<WRAP centeralign>//Figure 18. AD9684-500 FFT Data Capture Settings//</WRAP> | - The first item to configure in Visual Analog is the input clock frequency. This is the frequency of the input clock and NOT the decimated sample rate (if using decimation). Click in the ADC Data Capture block to open the settings. In this example, 500MHz is the input clock frequency. In addition, the DDC data must be selected under the Output Data section. DDC0 is being used in the AD9684 so this must be selected under the ADC Data Capture Settings.{{ :eval:AD9684_2ddcrealdec2_datacapturesettings.png?400 |}}<WRAP centeralign>//Figure 22. AD9684-500 FFT Data Capture Settings//</WRAP> |
| - In order to exclude the image frequency from the SFDR measurements, configure Visual Analog to remove the image from its calculations. This is done under the FFT Analysis settings. Under the User-Defined tab add a new row by clicking Add. Name it ‘Image’. Use a symbol such as the # and set the Freq to ‘-fund’. Set the Single-Side Band to 3 Bins and set it as ‘Spur, Exclude’. Once done, select the row, and then hit the Move Up button to place this new row just below the row with Fund.{{ :resources:eval:AD6674_2adc1ddccomplexdec2_fftanalysissettings.png?700 |}}<WRAP centeralign>//Figure 19. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP> | - In order to exclude the image frequency from the SFDR measurements, configure Visual Analog to remove the image from its calculations. This is done under the FFT Analysis settings. Under the User-Defined tab add a new row by clicking Add. Name it ‘Image’. Use a symbol such as the # and set the Freq to ‘-fund’. Set the Single-Side Band to 3 Bins and set it as ‘Spur, Exclude’. Once done, select the row, and then hit the Move Up button to place this new row just below the row with Fund.{{ :resources:eval:AD6674_2adc1ddccomplexdec2_fftanalysissettings.png?700 |}}<WRAP centeralign>//Figure 23. AD9684-500 FFT with 2 DDCs in Real Mode with Dec2 Enabled//</WRAP> |
| - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_1ddccomplexdec2.png?600 |}}<WRAP centeralign>//Figure 20. AD9684-500 FFT with 1 DDC in Complex ZIF Mode with Dec2 Enabled//</WRAP> | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ :resources:eval:AD9684_fft_1ddccomplexdec2.png?600 |}}<WRAP centeralign>//Figure 24. AD9684-500 FFT with 1 DDC in Complex ZIF Mode with Dec2 Enabled//</WRAP> |
| - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. A -1dBFS input signal will show as -2dBFS in Visual Analog. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. A -1dBFS input signal will show as -2dBFS in Visual Analog. |
| - To save the FFT plot do the following | - To save the FFT plot do the following |
| - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 21. Floating the FFT window//</WRAP> | - Click on the Float Form button in the FFT window{{ :resources:eval:fig13_floatform.png?nolink |}}<WRAP centeralign>//Figure 25. Floating the FFT window//</WRAP> |
| - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:AD9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 22. Saving the FFT//</WRAP> | - Click on File <m>right</m> Save Form As button and save it to a location of choice{{ :resources:eval:AD9684_fft_graph_saveformas.png |}}<WRAP centeralign>//Figure 26. Saving the FFT//</WRAP> |
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| * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. |
| * In VisualAnalog, Click on the Settings button in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos compliment by default). Repeat for the other channel. | * In VisualAnalog, Click on the Settings button in the **Input Formatter** block. Check that **Number Format** is set to the correct encoding (twos compliment by default). Repeat for the other channel. |
| * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure 23{{ :eval:AD9684_datapathsoftreset.png?nolink |}}<WRAP centeralign>//Figure 23. Issuing a data path soft reset through SPIController//</WRAP> | * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure 27{{ :eval:AD9684_datapathsoftreset.png?nolink |}}<WRAP centeralign>//Figure 27. Issuing a data path soft reset through SPIController//</WRAP> |
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| ** The FFT plot appears normal, but performance is poor. ** | ** The FFT plot appears normal, but performance is poor. ** |
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| ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** |
| * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 24.{{ :eval:AD9684_clockdetect.png?600 |}}<WRAP centeralign>//Figure 24. Clock Detection Status Register//</WRAP> | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure 28.{{ :eval:AD9684_clockdetect.png?600 |}}<WRAP centeralign>//Figure 28. Clock Detection Status Register//</WRAP> |
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