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resources:eval:ad9684-500ebz [13 Jan 2023 01:38] – [Device Setup - Full Bandwidth Mode] John Xavier Toledo | resources:eval:ad9684-500ebz [13 Jan 2023 02:42] (current) – [Device Setup - Full Bandwidth Mode] John Xavier Toledo | ||
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- The [[adi> | - The [[adi> | ||
- If the Device Manager does not show the [[adi> | - If the Device Manager does not show the [[adi> | ||
- | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector | + | - On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to connector |
- | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to J100. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, |
- | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, | + | - On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to J102. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, |
==== Visual Analog Setup ==== | ==== Visual Analog Setup ==== | ||
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==== Device Setup - Full Bandwidth Mode ==== | ==== Device Setup - Full Bandwidth Mode ==== | ||
- | - The settings in the ADCBase0 tab must be changed to configure the AD9684 | + | |
- | - The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | + | |
- | - The tuning step is equal to the output sample rate divided by 4096. | + | |
- | - tuning step = 500MSPS/ | + | |
- | - The translation frequency is equal to the output sample rate divided by 4*(decimation ratio). | + | |
- | - translation frequency = 500MSPS/(4*2) = 62500000 | + | |
- | - The DDC Phase Increment is equal to the translation frequency divided by the tuning step. | + | |
- | - DDC Phase Increment = 62500000/ | + | |
- | - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | + | |
- | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | + | |
==== Obtaining an FFT - Full Bandwidth Mode ==== | ==== Obtaining an FFT - Full Bandwidth Mode ==== | ||
+ | - The first item to configure in Visual Analog is the input clock frequency. | ||
+ | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | ||
+ | - Adjust the amplitude of the input signal so that the fundamental is at the -1.0 dBFS level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) | ||
+ | - To save the FFT plot do the following: | ||
+ | - Click on the Float Form button in the FFT window {{ : | ||
+ | - Click on File < | ||
==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ==== Device Setup - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ||
- | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDCs. In this example the AD9684 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. | + | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDCs. In this example the AD9684 is set up to use two DDCs (one per ADC channel) with real outputs and a decimation ratio of two. Set the Chip Application Mode in register 0x200 to Two Digital Down Converters and select the Only Real (I) Selected checkbox. |
- The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | - The DDC settings must be configured in ADCBase1, but first, the tuning step, translation frequency, and DDC Phase Increment must be calculated. | ||
- The tuning step is equal to the output sample rate divided by 4096. | - The tuning step is equal to the output sample rate divided by 4096. | ||
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- DDC Phase Increment = 62500000/ | - DDC Phase Increment = 62500000/ | ||
- Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | - Under DDCO CTRL and DDC1 CTRL in the ADCBase1 tab configure the DDCs to select 6dB Gain, Decimate by 4 Filter Selection (when in real mode this actually sets the AD9684 to Decimate by 2), Real (I) Output Only, Both Input Sample Selections to Channel A for DDC0 and Channel B for DDC1, and the DDC Phase Increment to the calculated value of 512 | ||
- | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | + | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : |
==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 2DDCs, Real Mode Decimate by 2 ==== | ||
- The first item to configure in Visual Analog is the input clock frequency. | - The first item to configure in Visual Analog is the input clock frequency. | ||
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the **Fund Power** reading in the left panel of the VisualAnalog FFT window.) Real DDC operation imposes ~0.7 dB loss on the input signal but does not impact the dynamic range. | ||
- | - To save the FFT plot do the following | + | - To save the FFT plot do the following: |
- | - Click on the Float Form button in the FFT window | + | - Click on the Float Form button in the FFT window {{ : |
- | {{ : | + | - Click on File < |
- | - Click on File < | + | |
==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Device Setup - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ||
- | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC. In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. | + | - The settings in the ADCBase0 tab must be changed to configure the AD9684 to use the DDC. In this example the AD9684 will be set up to use one DDCs with a complex ZIF output (NCO bypassed) and a decimation ration of two. Set the Chip Application Mode in register 0x200 to One Digital Down Converter and make sure the Only Real (I) Selected checkbox is **//NOT//** checked. |
- The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | - The DDC settings must be configured under DDC0 CTRL in the ADCBase1 tab configure the DDC to select Complex Mixer Selection, 0 Hz IF Mode, Decimate by 2 Filter Selection, Real (I) Input Sample Selection to Channel A for DDC0, and Complex (Q) Input Sample Selection to Channel B. | ||
- | - After changing DDC selections, perform a soft reset of the DDCs by checking and unchecking the box for DDC Soft Reset under the DDC Synchronization CTRL Reg (300). {{ : | + | |
==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ==== Obtaining an FFT - 2 ADCs, 1DDC, Complex ZIF Mode Decimate by 2 ==== | ||
- | - The first item to configure in Visual Analog is the input clock frequency. | + | - The first item to configure in Visual Analog is the input clock frequency. |
- | - In order to exclude the image frequency from the SFDR measurements, | + | - In order to exclude the image frequency from the SFDR measurements, |
- | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : | + | - Click the Run button in Visual Analog and you should see the capture data similar to the plot below. {{ : |
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. | - Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the “Fund Power” reading in the left panel of the VisualAnalog FFT window.) Complex DDC operation imposes ~1dB loss in the signal, but does not impact the dynamic range. | ||
- To save the FFT plot do the following | - To save the FFT plot do the following | ||
- | - Click on the Float Form button in the FFT window{{ : | + | - Click on the Float Form button in the FFT window{{ : |
- | - Click on File < | + | - Click on File < |
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* If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. | ||
* In VisualAnalog, | * In VisualAnalog, | ||
- | * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure | + | * Issue a **Data Path Soft Reset** through SPIController **Global** tab as shown in Figure |
** The FFT plot appears normal, but performance is poor. ** | ** The FFT plot appears normal, but performance is poor. ** | ||
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** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ** VisualAnalog displays a blank FFT when the RUN button is clicked ** | ||
- | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure | + | * Ensure that the clock to the ADC is supplied. Using SPIController **ADCBase0** tab the status of the clock can be read out. See figure |