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--- university:tools:pluto:users:understanding [10 Aug 2017 02:21] – Fixed typos, linked ZYNQ page Abhinav Uppal
+++ university:tools:pluto:users:understanding [14 Jan 2021 05:38] (current) – use xilinx> interwiki links Robin Getz
@@ Line 22: / Line 22: @@
   * Fully integrated phase-locked loops (PLLs) inside the AD9363 provide clocks and local oscillators for receive and transmit channels, and clocks for the ADC, DAC and output sample rate.
-The [[https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html|Xilinx Zynq All Programmable SoC]] (AP SoC) integrates the software programmability of an ARM-based processor with the hardware programmability of an FPGA, enabling hardware acceleration while integrating CPU, DSP, ASSP, and mixed signal functionality into a single device. Such devices feature a single-core ARM Cortex™-A9 processor mated with 28nm Artix®-7 based programmable logic, outfitted with commonly used hardened peripherals (USB, SPI, etc.)
+The [[xilinx>products/silicon-devices/soc/zynq-7000.html|Xilinx Zynq All Programmable SoC]] (AP SoC) integrates the software programmability of an ARM-based processor with the hardware programmability of an FPGA, enabling hardware acceleration while integrating CPU, DSP, ASSP, and mixed signal functionality into a single device. Such devices feature a single-core ARM Cortex™-A9 processor mated with 28nm Artix®-7 based programmable logic, outfitted with commonly used hardened peripherals (USB, SPI, etc.)

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