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university:tools:pluto:hacking:power_amp [09 Jul 2019 03:50]
Robin Getz add test results section
university:tools:pluto:hacking:power_amp [16 Jul 2019 20:15] (current)
Robin Getz [Test Results]
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 ====== Controlling External Devices on the ADALM-PLUTO ====== ====== Controlling External Devices on the ADALM-PLUTO ======
  
-<WRAP todo>This is work in progressneed to check the GPO sections on Pluto</​WRAP>​+While this was requested to better understand how to control external power amplifiers for various software to implement [[wp>Push-to-talk|push to talk]] (PTT), and ensure the PA was off during the Rx portion, this is good practice for any application which is just doing Rx or just doing Tx for best performance. Even you you are not concerned about controlling external devicesthis may be a good read for some (just skip the GPO discussions).
  
-While this was requested to better understand how to control external power amplifiers for various software ​to implement ​push to talkand ensure ​the PA was off during the Rx portionthis is good practice for any application ​which is just doing Rx or just doing Tx for best performance. Even you you are not concerned about controlling external devices, this may be a good read for some (just skip the GPO discussions).+There are two ways to implement ​General Purpose Output (GPO)Automatically (the easy way)or Software Controlled (which is handled later). 
  
 ===== Background ===== ===== Background =====
  
-The [[adi>​AD9363]] transceiver inside the ADALM-PLUTO includes an Enable State Machine (ENSM) that allows ​realtime ​control over the current state of the device. The device can be placed in several different states during normal operation, including:+The [[adi>​AD9363]] transceiver inside the ADALM-PLUTO includes an Enable State Machine (ENSM) that allows ​real time control over the current state of the device. The device can be placed in several different states during normal operation, including:
   * Wait — power save, synthesizers disabled   * Wait — power save, synthesizers disabled
   * Sleep — wait with all clocks and the BB PLL disabled   * Sleep — wait with all clocks and the BB PLL disabled
-  * Tx — Tx signal chain enabled (Rx signal chain powered down) +  * Time Division Duplex (TDD) Tx — Tx signal chain enabled (Rx signal chain powered down) 
-  * Rx — Rx signal chain enabled (Tx signal chain powered down) +  * Time Division Duplex (TDD) Rx — Rx signal chain enabled (Tx signal chain powered down) 
-  * FDD — Tx and Rx signal chains enabled+  * Frequency Division Duplex (FDD— Tx and Rx signal chains enabled, where both Tx and Rx can be used simultaneously at different frequencies.
   * Alert — synthesizers enabled   * Alert — synthesizers enabled
 +
 +In this document, we will mainly focus on the Frequency Division Duplex (FDD) mode and the Time Division Duplex (TDD) Tx & Rx modes.
  
 While the default settings are FDD mode (where Tx and Rx signal chains are always enabled), there are many use cases where TDD (Time Division Duplex) mode is beneficial. The ENSM has two control modes (1) SPI control and (2) pin control. If the TDD is a slotted system, where μsecond timing requirements must be met, pin control from a FPGA based state machine is normally used. When the TDD system is random, or push to talk, SPI control is possible. In SPI control mode, the ENSM is controlled asynchronously by writing to SPI registers to advance the current state to the next state. SPI control is considered asynchronous to the device or sample clock because the SPI clock can be derived from a different clock reference and can still function properly. The SPI control ENSM mode is recommended when real-time control of the synthesizers is not necessary. While the default settings are FDD mode (where Tx and Rx signal chains are always enabled), there are many use cases where TDD (Time Division Duplex) mode is beneficial. The ENSM has two control modes (1) SPI control and (2) pin control. If the TDD is a slotted system, where μsecond timing requirements must be met, pin control from a FPGA based state machine is normally used. When the TDD system is random, or push to talk, SPI control is possible. In SPI control mode, the ENSM is controlled asynchronously by writing to SPI registers to advance the current state to the next state. SPI control is considered asynchronous to the device or sample clock because the SPI clock can be derived from a different clock reference and can still function properly. The SPI control ENSM mode is recommended when real-time control of the synthesizers is not necessary.
  
-The AD9363 also include 4 ''​GPO_[0:​3]''​ General-Purpose Output pins. These are general-purpose logic output pins. These pins are designed to control other peripheral devices such as regulators and switches ​via the SPI bus, or they function as slaves for the internal AD9363 state machine. They can be configured to assert when the the Rx or Tx is active.+The AD9363 also include 4 ''​GPO_[0:​3]''​ General-Purpose Output pins. These are general-purpose logic output pins. These pins are designed to control other peripheral devices such as regulatorsswitches ​via the SPI bus, or they function as slaves for the internal AD9363 state machine. They can be configured to assert when the the Rx or Tx is active.
  
 More information about the [[adi>​AD9363]] can be found on the product page. More information about the [[adi>​AD9363]] can be found on the product page.
  
-===== ADLM-PLUTO implementation =====+===== ADALM-PLUTO implementation =====
  
 ==== VDD_GPO ==== ==== VDD_GPO ====
  
-The power connected to the ''​VDD_GPO''​ pin is 1.3 V The output voltage on the ''​GPO_[0:​3]''​ pins is expected to be ''​VDD_GPO × 0.8''​ (1.04 V) and ''​VDD_GPO''​ (1.30 V). With an output current of 10 mA (typical). If you connect regulators or switches, it may need to be level shifted to achieve the proper voltage control thresholds. ​+The power connected to the ''​VDD_GPO''​ pin is 1.3 V The output voltage on the ''​GPO_[0:​3]''​ pins is expected to be ''​VDD_GPO × 0.8''​ (1.04 V) and ''​VDD_GPO''​ (1.30 V). With an output current of 10 mA (typical). The off resistance of the GPO pins is 15 Ω. The on resistance of the GPO pins is 32 Ω. If you connect regulators or switches, it may need to be level shifted/have the drive strength increased ​to achieve the proper voltage control thresholds.
  
-With the 1.3 V ''​VDD_GPO''​ net, it is known that the AUX_ADC and AUX_DAC will not be functional.+With the 1.3 V ''​VDD_GPO''​ net, it is known/​understood ​that the AUX_ADC and AUX_DAC will not be functional.
  
 ==== Pinout ==== ==== Pinout ====
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 The [[./​hardware|schematic]] connects the ''​GPO_[0:​3]''​ pins to ''​GPO[0:​3]''​ nets and test points. The [[./​hardware|schematic]] connects the ''​GPO_[0:​3]''​ pins to ''​GPO[0:​3]''​ nets and test points.
  
-{{:​university:​tools:​pluto:​hacking:​pluto_gpo_pins.png?​400|}}+{{ :​university:​tools:​pluto:​hacking:​pluto_gpo_pins.png?​400 |}} 
 + 
 +Just connect these ''​GPO[0:​3]''​ pins to whatever you need to control.
  
 ==== Software ==== ==== Software ====
  
-There is a setup portion (if you are unsure of what these attributes do, check out the [[/​resources/​tools-software/​linux-drivers/​iio-transceiver/​ad9361-customization|documentation]]:​+There is a setup portion (if you are unsure of what these attributes do, check out the [[/​resources/​tools-software/​linux-drivers/​iio-transceiver/​ad9361-customization|documentation]]: ​((If you want to delay the assertion of these pins by ''​n''​ μs, that can be done with the ''​gpo0-rx-delay-us''​ or ''​gpo0-tx-delay-us''​ attributes (which we don't cover here)) ​
   - set up the part in TDD mode (''​0''​ is TDD mode, ''​1''​ is FDD mode):<​code>​iio_attr -a -D ad9361-phy adi,​frequency-division-duplex-mode-enable 0</​code>​   - set up the part in TDD mode (''​0''​ is TDD mode, ''​1''​ is FDD mode):<​code>​iio_attr -a -D ad9361-phy adi,​frequency-division-duplex-mode-enable 0</​code>​
-  - set up ''​GPO_0''​ to assert when in Tx mode<​code>​iio_attr -a -D ad9361-phy adi,gpo0_slave_tx_enable ​1</​code>​+  - set up ''​GPO_0''​ to assert when in Tx mode<​code>​iio_attr -a -D ad9361-phy adi,gpo0-slave-tx-enable ​1</​code>​
   - write the new configuration to the part <​code>​iio_attr -a -D ad9361-phy ​ initialize 1</​code>​   - write the new configuration to the part <​code>​iio_attr -a -D ad9361-phy ​ initialize 1</​code>​
  
-Verify ​things are the way you think, by checking the ''​_available''​ attribute, and making sure it is rx or tx only.<​code>​iio_attr -u ip:​192.168.2.1 ​-d ad9361-phy ensm_mode_available+Verify the setup is in TDD mode, by checking the ''​ensm_mode_available''​ attribute, and making sure it includes ''​rx''​ and ''​tx''​ and not ''​fdd''​.<​code>​iio_attr --d ad9361-phy ensm_mode_available
 dev '​ad9361-phy',​ attr '​ensm_mode_available',​ value :'​sleep wait alert rx tx pinctrl'</​code>​ dev '​ad9361-phy',​ attr '​ensm_mode_available',​ value :'​sleep wait alert rx tx pinctrl'</​code>​
  
 Then there is a run time configuration that is needed. Then there is a run time configuration that is needed.
-  - To set the part into Receive only mode:<​code>​iio_attr -u ip:​192.168.2.1 ​-d ad9361-phy ensm_mode rx</​code>​ +  - To set the part into Receive only mode:<​code>​iio_attr --d ad9361-phy ensm_mode rx</​code>​ 
-  - To set the part into Tx only mode:<​code>​iio_attr -u ip:​192.168.2.1 ​-d ad9361-phy ensm_mode tx</​code>​+  - To set the part into Tx only mode:<​code>​iio_attr --d ad9361-phy ensm_mode tx</​code>​ 
 + 
 +When you change from Rx mode to Tx mode, any of the four pins will assert/​de-assert.
  
 <WRAP important>​It should be noted that trying to capture a buffer (ie Rx) while in Tx mode will pause/hang until timed out. And sending a buffer (Tx) while in Rx mode will also pause/hang. Cancelling things will return.</​WRAP>​ <WRAP important>​It should be noted that trying to capture a buffer (ie Rx) while in Tx mode will pause/hang until timed out. And sending a buffer (Tx) while in Rx mode will also pause/hang. Cancelling things will return.</​WRAP>​
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 ==== Test Results ==== ==== Test Results ====
  
-<​WRAP ​WARNING>Still need to test</​WRAP>​+A small script on the Pluto SDR (or host) will demonstrate:​ 
 + 
 +<​xterm>​ 
 +#!/bin/sh 
 + 
 +# Setup : Put into TDD mode, and setup GPO0 and GPO1 
 +iio_attr -q -a -D ad9361-phy adi,​frequency-division-duplex-mode-enable 0 
 +iio_attr -q -a -D ad9361-phy adi,​gpo0-slave-rx-enable 1 
 +iio_attr -q -a -D ad9361-phy adi,​gpo1-slave-tx-enable 1 
 +iio_attr -q -a -D ad9361-phy ​ initialize 1 
 + 
 +while [ 1 ] ; do 
 +  iio_attr -q -a -d ad9361-phy ensm_mode rx 
 +  # capture buffer 
 +  iio_attr -q -a -d ad9361-phy ensm_mode tx 
 +  # transmit buffer 
 +done 
 +</​xterm>​ 
 + 
 +by placing a scope on the GPO0 and GPO1 pins, you can see the levels switch, as the Pluto transitions between Receive and Transmit. 
 + 
 +{{ :​university:​tools:​pluto:​hacking:​gpo_rx_tx.png?​600 |}} 
 + 
 +<​WRAP ​round help>While this shows the Rx/Tx switching in 30-35ms or so, this is based on **software** control over SPI, running in an interpreted bash shell. Doing things in a C application,​ would make things faster, and doing things via pin control (via a state machine in the FPGA) can make things sub ~30 μs between Rx and Tx swaps to handle slotted specifications like LTE. IF you need things ​to go faster - just ask. 
 +</​WRAP>​ 
 + 
 +OK, someone asked for the C code - it's pretty trivial, just longer. You will need to change the uri, and put in proper error checking. 
 + 
 +<​code>​ 
 +#include <​stdio.h>​ 
 +#include <​iio.h>​ 
 +#include <​unistd.h>​ 
 +#include <​stdio.h>​ 
 +#include <​signal.h>​ 
 + 
 + 
 +volatile sig_atomic_t stop = 0; 
 + 
 +void inthand(int signum) { 
 +        stop = 1; 
 +
 + 
 +int main(int argc, char **argv) 
 +
 +        struct iio_context *ctx; 
 +        struct iio_device *dev; 
 +        struct iio_channel *ch; 
 +        const char* val_str; 
 +        ssize_t ret = 0; 
 +        char buf[256]; 
 + 
 +        signal(SIGINT,​ inthand); 
 + 
 +        /* Create IIO Context */ 
 +        ctx = iio_create_context_from_uri("​usb:​1.3.5"​);​ 
 + 
 +        /* Find IIO device in current context */ 
 +        dev = iio_context_find_device(ctx,​ "​ad9361-phy"​);​ 
 + 
 +        /* Write into the IIO debug attributes */ 
 +        iio_device_debug_attr_write_bool(dev,​ "​adi,​frequency-division-duplex-mode-enable",​ 0); 
 +        iio_device_debug_attr_write_bool(dev,​ "​adi,​gpo0-slave-rx-enable",​ 1); 
 +        iio_device_debug_attr_write_bool(dev,​ "​adi,​gpo1-slave-tx-enable",​ 1); 
 +        iio_device_debug_attr_write_bool(dev,​ "​initialize",​ 1); 
 +         
 +        while (!stop) { 
 +                ret++; 
 +                iio_device_attr_write(dev,​ "​ensm_mode",​ "​rx"​);​ 
 +                iio_device_attr_write(dev,​ "​ensm_mode",​ "​tx"​);​ 
 +        } 
 +        iio_context_destroy(ctx);​ 
 +        printf("​iteration = %li\n",​ ret); 
 +        return EXIT_SUCCESS;​ 
 +
 +</​code>​ 
 + 
 +Over USB, you get:<​xterm>​ 
 + time ./foo  
 +^Citteration = 2693 
 + 
 +real 0m5.283s 
 +</​xterm>​ 
 + 
 +or about 0.980876346 ms per Rx/Tx slot. 
 + 
 +^ Platform ​ ^ transport ^ Infrastructure ​ ^  Timing ^ 
 +| host | USB | shell | 80ms | 
 +| host | USB | C code | 0.6 to 1.3 ms | 
 +| pluto | local | shell | 30-35ms | 
 +| pluto | local | C Code | 0.2 to 0.6 ms |  
 + 
 +Again, these are representative numbers for software control, faster is possible with pin control. 
 +===== Testing in IIO Oscilloscope ===== 
 + 
 +The [[/​resources/​tools-software/​linux-software/​fmcomms2_advanced_plugin#​axillary_io_adc_dac_control_io_temp_sensor|Advanced Tab]] indicates how to control these in the IIO oscilloscope. 
 + 
  
university/tools/pluto/hacking/power_amp.1562637057.txt.gz · Last modified: 09 Jul 2019 03:50 by Robin Getz