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Controlling External Devices on the ADALM-PLUTO

While this was requested to better understand how to control external power amplifiers for various software to implement push to talk, and ensure the PA was off during the Rx portion, this is good practice for any application which is just doing Rx or just doing Tx for best performance. Even you you are not concerned about controlling external devices, this may be a good read for some (just skip the GPO discussions).


The AD9363 transceiver inside the ADALM-PLUTO includes an Enable State Machine (ENSM) that allows realtime control over the current state of the device. The device can be placed in several different states during normal operation, including:

  • Wait — power save, synthesizers disabled
  • Sleep — wait with all clocks and the BB PLL disabled
  • Tx — Tx signal chain enabled (Rx signal chain powered down)
  • Rx — Rx signal chain enabled (Tx signal chain powered down)
  • FDD — Tx and Rx signal chains enabled
  • Alert — synthesizers enabled

While the default settings are FDD mode (where Tx and Rx signal chains are always enabled), there are many use cases where TDD (Time Division Duplex) mode is beneficial. The ENSM has two control modes (1) SPI control and (2) pin control. If the TDD is a slotted system, where μsecond timing requirements must be met, pin control from a FPGA based state machine is normally used. When the TDD system is random, or push to talk, SPI control is possible. In SPI control mode, the ENSM is controlled asynchronously by writing to SPI registers to advance the current state to the next state. SPI control is considered asynchronous to the device or sample clock because the SPI clock can be derived from a different clock reference and can still function properly. The SPI control ENSM mode is recommended when real-time control of the synthesizers is not necessary.

The AD9363 also include 4 GPO_[0:3] General-Purpose Output pins. These are general-purpose logic output pins. These pins are designed to control other peripheral devices such as regulators and switches via the SPI bus, or they function as slaves for the internal AD9363 state machine. They can be configured to assert when the the Rx or Tx is active.

More information about the AD9363 can be found on the product page.

ADLM-PLUTO implementation


The power connected to the VDD_GPO pin is 1.3 V The output voltage on the GPO_[0:3] pins is expected to be VDD_GPO × 0.8 (1.04 V) and VDD_GPO (1.30 V). With an output current of 10 mA (typical). If you connect regulators or switches, it may need to be level shifted to achieve the proper voltage control thresholds.

With the 1.3 V VDD_GPO net, it is known that the AUX_ADC and AUX_DAC will not be functional.


The schematic connects the GPO_[0:3] pins to GPO[0:3] nets and test points.


There is a setup portion (if you are unsure of what these attributes do, check out the documentation:

  1. set up the part in TDD mode (0 is TDD mode, 1 is FDD mode):
    iio_attr -a -D ad9361-phy adi,frequency-division-duplex-mode-enable 0
  2. set up GPO_0 to assert when in Tx mode
    iio_attr -a -D ad9361-phy adi,gpo0_slave_tx_enable 1
  3. write the new configuration to the part
    iio_attr -a -D ad9361-phy  initialize 1

Verify things are the way you think, by checking the _available attribute, and making sure it is rx or tx only.

iio_attr -u ip: -d ad9361-phy ensm_mode_available
dev 'ad9361-phy', attr 'ensm_mode_available', value :'sleep wait alert rx tx pinctrl'

Then there is a run time configuration that is needed.

  1. To set the part into Receive only mode:
    iio_attr -u ip: -d ad9361-phy ensm_mode rx
  2. To set the part into Tx only mode:
    iio_attr -u ip: -d ad9361-phy ensm_mode tx

It should be noted that trying to capture a buffer (ie Rx) while in Tx mode will pause/hang until timed out. And sending a buffer (Tx) while in Rx mode will also pause/hang. Cancelling things will return.

university/tools/pluto/hacking/power_amp.1562636184.txt.gz · Last modified: 09 Jul 2019 03:36 by Robin Getz