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This version (02 Jun 2022 18:07) was approved by Travis Collins.The Previously approved version (02 Jun 2022 18:06) is available.Diff

Accessing Pluto's FPGA Over JTAG

Connecting to Pluto over JTAG requires a standard JTAG programmer from Xilinx or a simplier solution like the JTAG-HS3+JTAGUART programmer. We will be using the JTAG-HS3+JTAGUART in this guide.

First, open up PlutoSDR's case and locate the JTAG_BOOT connector holes on the bottom left portion of the PCB. Using an 8 pin ribbon cable from your JTAG programmer connect to those pins as shown in the figure below.

After the JTAG programmer is connected, provide power to PlutoSDR using either of its USB connectors. Once powered the D5 led should illuminate to signal the JTAG connection to the programmer is alive. This will appear like the figure below.

Next we can go into vivado and check the hardware manager for connectivity. This can be done with xsct as follows: 

tcollins@winston:/tmp$ xsct
rlwrap: warning: your $TERM is 'xterm' but rlwrap couldn't find it in the terminfo database. Expect some problems.
                                                                                                                    
****** Xilinx Software Commandline Tool (XSCT) v2017.4.1
  **** Build date : Jan 30 2018-15:42:35
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.


xsct% connect -host localhost -port 3121                                                                            
tcfchan#0                                                                                                           
xsct% targets                                                                                                       
  1  APU
     2  ARM Cortex-A9 MPCore #0 (Running)
     3  ARM Cortex-A9 MPCore #1 (Running)
  4  xc7z010
xsct%

Alternatively in the GUI, PlutoSDR should appear as so:

Unbricking PlutoSDR

If for some reason PlutoSDR does not boot, if the firmware update failed for example, the device will appear in DFU mode (1 solid LED and no blinking LED) but not actually boot into DFU. This happens when u-boot or the FSBL is corrupted. This is unlikely but can happen. To fix this you can leverage the JTAG bootstrap zip part of each release. To do so perform the following:

  1. Plug in JTAG as documented above into Pluto and verify you can connect with Vivado
  2. Download the JTAG bootstrap zip from the firmware release page (plutosdr-jtag-bootstrap-<Firmware Version>.zip)
  3. Unzip the zip then source the run.tcl inside with xmd from the Xilinx tools (xmd -tcl run.tcl). We are done with JTAG now
  4. Next plugin a USB cable to the UART port of the ADALM-UARTJTAG connector and open a serial session (Putty or screen or …)
  5. At this point you should have access to the u-boot menu. Directly from u-boot serial console type: run dfu_sf. This will put PlutoSDR into DFU mode.
  6. Now plugin PlutoSDR's data USB port to your PC and it should appear as a DFU device
  7. Flash the firmware as usual with the DFU utils as documented here
university/tools/pluto/devs/fpga.txt · Last modified: 02 Jun 2022 18:07 by Travis Collins

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