Description | Test Steps | Steps Resources | Expected Results |
Checking Group Channels and Patterns: Use PP as output. Binary Counter | 1.1 Create a 4-channel group. Enable channels DIO0 to DIO3. Then click “Group” and double click on the channel indicators on the plot, DIO 0 to DIO 3, then click “Done”. Change pattern to Binary Counter. |  | The interface should look like in the “Step Resources” picture (left side). |
1.2 Open logic analyzer. Make a group with channels DIO0 to DIO3. Once grouped, add parallel for the decoder. Make sure to select correct data lines in the parallel decoder settings. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. |
1.3 Check the frequency of each channel through oscilloscope. Connect DIO0 to scopech1+. Enable built-in measurement for frequency. |  | Frequency shown should be 2.4 KHz to 2.6 KHz, corresponding to set clock frequency/2. |
1.4 Connect DIO1 to scopech1+. Enable built-in measurement for frequency. |  | Frequency shown should be 1.24 KHz to 1.27 KHz, corresponding to set clock frequency/4. |
1.5 Connect DIO2 to scopech1+. Enable built-in measurement for frequency. |  | Frequency shown should be 620 Hz to 630 Hz, corresponding to set clock frequency/8. |
1.6 Connect DIO3 to scopech1+. Enable built-in measurement for frequency. |  | Frequency shown should be 310 Hz to 315 Hz, corresponding to set clock frequency/16. |
Random | 2.1 Change pattern to Random. Frequency: 5KHz |  | The interface should look like in the “Step Resources” picture (left side). |
2.2 Monitor through logic analyzer. Use parallel as decoder. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. The same hexadecimal equivalents should be seen in logic analyzer. |
2.3 Change frequency: 100 KHz |  | The interface should look like in the “Step Resources” picture (left side). There should be new set of data and hexadecimal equivalents. |
2.4 Monitor through logic analyzer. Use parallel as decoder. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. The same hexadecimal equivalents should be seen in logic analyzer. |
Number pattern | 3.1 Change pattern to Number pattern. Set number to 3. Enable DIO 4 and set to Clock pattern with 5kHz frequency. Do not add DIO 4 to group, keep it as individual channel. |  | The interface should look like in the “Step Resources” picture (left side). |
3.2 Monitor through logic analyzer. Enable DIO 4 as individual channel. Use parallel as decoder. Set data lines to DIO 0 to DIO 3 and set clock line to DIO 4. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. The same number is seen in logic analyzer. Number: 3 |
3.3 Change number to 14. In the plot, it will show the hexadecimal equivalent which is E. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. The same hexadecimal equivalent is seen in logic analyzer. Hexadecimal equivalent: E |
3.4 Add channels DIO4 to DIO7 to the group. It will now be an 8-channel group. Change number to 254. The plot will show the hexadecimal equivalent which is FE. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. The same hexadecimal equivalent is seen in logic analyzer. Hexadecimal equivalent: FE |
Gray Counter | 4.1 Change pattern to Gray Counter. Disable DIO 8. |  | The interface should look like in the “Step Resources” picture (left side). |
4.2 Monitor through logic analyzer. Choose parallel for the decoder. Set Clock line as X. |  | The plot in the logic analyzer should resemble the plot seen in the pattern generator. One bit change per clock cycle. |
UART | 5.1 Dissolve current group channel. Enable DIO 0 channel and double click on the channel indicator on the plot. Change channel pattern to UART. Set parameters: Baud: 9600, Stop bit: 1, no parity, Data to send: ‘HELLO’. |  | The interface should look like in the “Step Resources” picture (left side). |
5.2 Monitor the channel in the logic analyzer. Use UART as decoder. Set Baud: 9600, Data bits: 8, no parity. |  | The interface should look like in the “Step Resources” picture (left side). |
5.3 Change set parameters: Baud: 115200, Stop bit: 1, even parity, Data to send: ‘HI’. |  | The interface should look like in the “Step Resources” picture (left side). |
5.4 Monitor the channel in the logic analyzer. Use UART as decoder. Set Baud: 115200, Data bits: 8, even parity. |  | The interface should look like in the “Step Resources” picture (left side). |
5.5 Change set parameters: Baud: 115200, Stop bit: 1, odd parity, Data to send: ‘HI’. |  | The interface should look like in the “Step Resources” picture (left side). |
5.6 Monitor the channel in the logic analyzer. Use UART as decoder. Set Baud: 115200, Data bits: 8, odd parity. |  | The interface should look like in the “Step Resources” picture (left side). |
SPI | 6.1 Disable DIO 0. Enable and select DIO5 to DIO7 to create a 3-channel group. Change pattern to SPI. Set the following parameters: Bytes per frame: 2, inter frame space: 3, Data: ABCD1234. |  | The interface should look like in the “Step Resources” picture (left side). |
6.2 Monitor the channel through logic analyzer. Use SPI as decoder. Refer to steps resources picture for the configuration of logic analyzer. |  | The interface should look like in the “Step Resources” picture (left side). |
6.3 Change the following parameters: Bytes per frame: 1, inter frame space: 4, Data: ABCD1234. |  | The interface should look like in the “Step Resources” picture (left side). |
6.4 Monitor the channel through logic analyzer. Use SPI as decoder. Refer to steps resources picture for the configuration of logic analyzer. |  | The interface should look like in the “Step Resources” picture (left side). |
I2C | 7.1 Dissolve current group channel. Enable and select DIO0 and DIO1 to create a 2-channel group. Change pattern to I2C. Set the following parameters: Address: 72, Inter frame space: 3, Data: ABCD1234. |  | The interface should look like in the “Step Resources” picture (left side). |
7.2 Monitor the channel through logic analyzer. Use I2C as decoder. Refer to steps resources picture for the configuration of logic analyzer. |  | The interface should look like in the “Step Resources” picture (left side). |
Pulse Pattern | 8.1 Change pattern to Pulse Pattern. Set the following parameters: Low: 5, High: 1, Counter Init: 0, Delay: 10, Number of Pulses: 5. |  | The interface should look like in the “Step Resources” picture (left side). |
7.2 Monitor the channels through logic analyzer. Refer to steps resources picture for the configuration of logic analyzer. |  | The interface should look like in the “Step Resources” picture (left side). |