Description | Test Steps | Steps Resources | Expected Results |
Checking Channel's Trigger Function | 1. Enable channel DIO0 and DIO1 on Logic analyzer, on the settings menu set sample rate to 50ksps and add a delay ex. -142 samples. On Pattern generator, enable DIO1, set the following parameter: Pattern: clock, Frequency: 100Hz, Phase: 0 degrees and Duty Cycle: 50%. On Digital IO instrument, set DIO0 as output |    | The interface should look like in the “Step Resources” picture (left side). Additional signals from the pattern generator and Logic analyzer from DIO2 to DIO15 at different frequencies will be better. |
Rising edge trigger | 2. Set DIO0’s trigger to rising edge configuration, run Digital IO, pattern generator and logic analyzer instrument. Change DIO0’s output from 0 to 1 from the Digital IO’s instrument |  | The logic analyzer should initiate a capture |
Falling edge trigger | 3. Set DIO0’s trigger to falling edge configuration and run both pattern generator and logic analyzer. Change DIO0’s output from 1 to 0 from the Digital IO’s instrument | | The logic analyzer should initiate a capture |
Any edge trigger | 4. Set DIO0’s trigger to any edge configuration and run both pattern generator and logic analyzer. Change DIO0’s output either from 1 to 0 or 0 to 1 from the Digital IO’s instrument |  | The logic analyzer should initiate a capture |
Low trigger | 5. Set DIO0’s Low configuration and run both pattern generator and logic analyzer. Set DIO0’s output to 0 |  | The logic analyzer should continuously capture the signal |
High Trigger | 6. Set DIO0’s trigger to high configuration and run both pattern generator and logic analyzer. Set DIO0’s output to 1 |  | The logic analyzer should continuously capture the signal |
7. Repeat steps 1 to 6 using DIO1 to DIO15 as triggers in the logic analyzer and Digital IO instrument and the remaining DIO channel as the signal to be captured of using Pattern generator | | The results should all be the same |
Testing External Triggers | 1. On Digital IO instrument set DIO0 as output. No changes on Pattern Generator. On Logic Analyzer’s trigger menu, turn on the External trigger. Select source as External Trigger In. |   | The interface should look like in the “Step Resources” pictures. Turning on the External Trigger should automatically turn off the triggers set on every DIO channels if there are any. |
2. Connect Trigger in 1 to DIO0 |  | |
Rising Edge Trigger | 3. Set External 1’s trigger to rising edge configuration, run Digital IO, pattern generator and logic analyzer instrument. Change DIO0’s output from 0 to 1 from the Digital IO instrument |  | The logic analyzer should initiate a capture |
Falling Edge Trigger | 4. Set External 1’s trigger to falling edge configuration, run Digital IO, pattern generator and logic analyzer instrument. Change DIO0’s output from 1 to 0 from the Digital IO instrument | | The logic analyzer should initiate a capture |
Any Edge Trigger | 5. Set External 1’s trigger to any edge configuration, run Digital IO, pattern generator and logic analyzer instrument. Change DIO0’s output from 1 to 0 or 0 to 1 from the Digital IO instrument |  | The logic analyzer should initiate a capture |
Low Trigger | 6. Set External 1’s trigger to low trigger configuration, run Digital IO, pattern generator and logic analyzer instrument. Set DIO0’s output to 0 from the Digital IO instrument |  | The logic analyzer should continuously capture the signals |
High Trigger | 7. Set External 1’s trigger to high trigger configuration, run Digital IO, pattern generator and logic analyzer instrument. Set DIO0’s output to 1 from the Digital IO instrument |  | The logic analyzer should continuously capture the signals. |
Testing Oscilloscope Source External Trigger | 8. In Logic analyzer enable External trigger and set Source to Oscilloscope | | The logic anayzer should initiate a capture when the Oscilloscope is triggered. |
9. Connect W1 to 1+ and GND to 1- and generate a Sine Waveform with 2V peak-to-peak amplitude and 200Hz frequency. Set the Oscilloscope trigger to normal and Condition to Rising Edge. | | The Oscilloscope should be triggered when the two blue Trigger cursors are intersected on the rising edge of the signal. |
10. Run Signal Generator, Oscilloscope and Logic analizer and verify if the Logic analyzer is triggered at the same time with the Oscilloscope. |  | If you drag the horizontal cursor in the Oscilloscope window above or below the signal, it should be in Waiting state, and Logic analyzer will be Waiting too. |
11. Repeat steps 9-11 for each condition of the trigger available in Oscilloscope | | Logic Analyzer and Oscilloscope should capture signals simultaneously and be in Waiting state at the same time. |
Testing the Trigger Modes | 1. On Pattern Generator, enable DIO2 and then set it to clock pattern 5KHz frequency. On Logic Analyzer, enable DIO0, DIO1, and DIO2. Set DIO0 and DIO1 trigger to both HIGH. Disable External trigger. |  | The interface should look like in the “Step Resources” pictures. Turning on the External Trigger should automatically turn off the triggers set on every DIO channels if there are any. |
2. On Digital IO instrument set DIO0 and DIO1 as output. |  | |
OR Mode | 3. On Logic Analyzer’s trigger configuration, set the trigger logic to OR. On Digital IO instrument, Set DIO0’s output to 0 and DIO1’s output to 0. Run Digital IO, Pattern Generator and Logic Analyzer Instrument |  | The logic analyzer should be on waiting mode and not capture any signal. |
4. On Digital IO instrument, Set DIO0 or DIO1’s output to 1. |  | The logic analyzer should start capturing signal when either of the DIO0 or DIO1 is HIGH. |
AND Mode | 5. On Logic Analyzer’s trigger configuration, set the trigger logic to AND. On Digital IO instrument, Set DIO0’s output to 0 and DIO1’s output to 1. Run Digital IO, Pattern Generator and Logic Analyzer Instrument |  | The logic analyzer should be on waiting mode and not capture any signal. |
6. On Digital IO instrument, Set DIO0’s and DIO1’s output to 1. |  | The logic analyzer should start capturing signal only when DIO0 and DIO1 are HIGH |
Checking Channel's Clock Signal Measurement Accuracy | 1. Enable channel DIO0, on the settings menu set sample rate to 50ksps, enable the cursor. On Pattern generator’s DIO0, set the following parameter: Pattern: clock, Frequency: 100Hz, Phase: 0 degrees and Duty Cycle: 50%. |  | Refer to the step resource picture |
2. Move the cursors to the consecutive rising edges or consecutive falling edges |  | The data measured by the cursor should be close to ∆t: 10ms and 1/∆t: 100Hz |
3. Enable Lock cursor feature and measure the next edges |  | The data measured by the cursor should be close to ∆t: 10ms and 1/∆t: 100Hz |
4. Set logic analyzer’s settings to sample rate: 100Msps, position: 0s. Set pattern generator DIO0’s parameters to: Pattern: clock, Frequency: 2.5MHz, Phase: 0 degrees and Duty Cycle: 50%. |  | Refer to the step resource picture |
5. Move the cursors to the consecutive rising edges or consecutive falling edges |  | The data measured by the cursor should be close to ∆t: 400ns and 1/∆t: 2.5MHz |
6. Enable Lock cursor feature and measure the next edges | | The data measured by the cursor should be close to ∆t: 400ns and 1/∆t: 2.5MHz |
7. Set logic analyzer’s settings to sample rate: 20ksps. Set pattern generator DIO0’s parameters to: Pattern: clock, Frequency: 100Hz, Phase: 0 degrees and Duty Cycle: 70%. |  | Refer to the step resource. |
8. Move the cursors to the rising and falling edge of the upper limit |  | The data measured by the cursor should be close to ∆t: 7ms |
9. Enable Lock cursor feature and measure the next edges | | The data measured by the cursor should be close to ∆t: 7ms |
10. Move the cursors to the falling and rising edge of the lower limit |  | The data measured by the cursor should be close to ∆t: 3ms |
11. Enable Lock cursor feature and measure the next edges | | The data measured by the cursor should be close to ∆t: 3ms |
12. Repeat steps 1 to 7 using DIO1 to DIO15 of both pattern generator and logic analyzer | | The results should all be the same |