1. Start digital IO instrument
2. Generate clock signals on channels 0 and 8
In the digitalIO the group as well as channel 8 should have a red highlight indicating that the pattern generator has ownership of the channels.
The user cannot interact with those channels. Logic analyzer shows clock signal correctly generated at channels 0 and 8
3. Connect channel 10 to channel 11
4. Set channel 10 as output and channel 11 as input
5. Modify channel 10 output state
Channel 11 input state follows channel 10 output state
Rest of the channels work properly. The user can set direction and output state and can read input state
6. While running, set a clock signal on channel 10 in the pattern generator
Channel 10 has a red highlight, the user cannot interact with it anymore. Channel 11 input state might flicker indicating that a signal can be read from channel 11.
Logic analyzer shows a new clock signal generated at channel 10 which can also be read on channel 11
7. Stop the pattern generator
Red highlight is removed from the digitalIO, the channels now work properly.