The objective of this activity is to explore some of the basic circuit blocks typically used in buck and boost converters. We'll operate these blocks to the point where they are “bucking” a high voltage to a low voltage and “boosting” a low voltage to a high voltage, and examine the open-loop properties of these modes of operation. We will also discuss the difference between synchronous and non-synchronous circuits, and continuous conduction mode versus discontinuous conduction modes. We'll start out by controlling these circuits by directly controlling the duty cycle of the switches, and then introduce the idea of peak current control, in which the switch that “charges” the inductor is turned on by a clock signal, and turned off when the inductor current reaches a certain level. Subsequent exercises will actively control these circuits in order to produce an accurate, stable output voltage that is insensitive to changes in input and output conditions.
The Activity: Buck Converter Basics lab activity was a first look into the operation of a very simple (and not very high performance) buck converter. The exercise details the operation of the ideal buck converter shown in Figure 1.
Figure 1. Ideal Buck Converter
A simple expression for output voltage as a function of input voltage and the duty cycle, is then derived:
This is followed by circuit construction, measurements of the open-loop properties of the circuit, and finally, “closing the loop” so that the output voltage remains constant, at the desired voltage, regardless of changes in loading.
This exercise will expand on those concepts, deriving a converter that “boosts” a low voltage to a high voltage. We will also design a more practical open-loop buck converter, and introduce a circuit that controls peak inductor current, rather than duty cycle. Subsequent exercises will close the loop around these circuits and examine loop stability and time-domain response. An appendix covers practical aspects of switching converter design such as current sensing, timing generation, selection of MOSFETs and diodes, and gate drive circuitry.
* (This exercise will use the term “ideal” extensively. A more accurate term would be “almost ideal” - LTspice requires finite numbers in certain locations - switch on and off resistances can't be zero or infinity, so we're using values small enough and large enough to have negligible impact on the results.)
Open the Boost_Concept.asc LTSpice file. Notice the differences between this circuit and the buck converter:
As with the buck basics lab, let's keep two things in mind at all times:
The figure below shows the “charge” state of the circuit’s operation, where S1 is closed and S2 is open.
Figure 2. Boost Converter Charge
When S1 closes, the left-hand side of the inductor is connected to the 5V supply, and the right-hand side is connected to ground. This means the voltage across the inductor is simply the 5V supply. This “charges” the inductor with a current that ramps up with a positive slope of:
Note: The polarity of the voltage across the inductor is arbitrary, we're using the convention that a positive voltage is one that causes an increase in energy stored in the inductor.
The next figure shows the other state, with S1 open and S2 closed.
Figure 3. Boost Converter Discharge
When S2 closes, the left-hand side of inductor L1 is still connected to Vin, while the right-hand side is now connected to Vout. The current through L1 is now flowing to the output, and decreasing with a negative slope of:
Similar to the buck converter basics activity 1 the “freq” and “duty” parameters set the frequency of the switching to 25kHz and the duty cycle of the voltages imposed on this switch node (sw_node) to 50%. That is, the righthand side of the inductor spends half of the time connected to ground (charging phase), and half of the time connected to the output (discharging phase). Run the simulation, and probe sw_node, Vout, and the current through inductor L1. Zoom in toward the end of the run after the startup transient damps out (after 8ms). (You can right-click, Auto range y-axis to line up the two waveforms.)
Figure 4. Boost Converter Switch Node, inductor current, and Output
Observe the peak and valley of the waveform I(L1) (green waveform), noting the current ripple. Using the cursors from peak to peak, we can observe that the inductor is charging and discharging linearly (with the period of 1/25kHz, or 40us, with a duty cycle of 50% making ts1 and ts2 20us each).
The output voltage is almost exactly 10V - double the input voltage - with a small ripple imposed. Verify that the previously solved equations are true, using the cursors to measure the inductor current waveforms.
For the “charge” phase:
And for the “discharge” phase:
Revisiting the concept of zero DC across an inductor, how can we find the output voltage of a boost converter knowing the input voltage, frequency, and duty cycle? “Zero DC across an inductor” means that over a long period of time, the average volt-second product is zero. Thus:
Where tS1 is the time that S1 is closed, tS2 is the time that S2 is closed. Rearranging, we see that:
is the duty cycle of the switch node, we can rewrite the expression for VOUT as a function of duty cycle:
Since our duty cycle is based off ts1 and ts2, and the duty cycle is always between 0% and 100%, the above equation demonstrates that the average output voltage is always equal or larger than the input voltage, a basic property of a boost converter, and at a 50% duty cycle, the output voltage is double the input voltage.
Now change the duty cycle in the simulation and re-run. The following are screenshots show the output voltage at 20% duty cycle(expected output of 6.25V) and 80% duty cycle(expected output of 25V).
Figure 5. Boost converter output with a duty cycle of 20%
Figure 6. Boost converter output with a duty cycle of 80%
Can you boost to an arbitrarily high voltage? See Appendix: “Extreme Boosting” to find out.
So far we've operated the boost circuit unloaded. In this condition, the duty cycle to boost factor relationships held true, but what happens if you start to draw current from the output (as you would in a practical circuit - after all, a power supply exists to power stuff!) Furthermore, consider the boost converter's output switch (S2). If we look at the current waveform and the voltage waveform of the unloaded circuit, we see that for part of the cycle, the inductor current goes negative, and when this occurs, the output voltage is ramping DOWN! This seems counterproductive for a boost converter, doesn't it? This mode of operation has a name - “Forced Continuous Conduction Mode”. It is forced because the switches always impose a voltage across the inductor, so its current is always either ramping up or down.
Next, connect the 25 ohm load resistor to the output node (drawing an average current of 0.4 amps from the 10V output). Note that the impact on the output voltage is minimal, and the inductor current is still ramping up and down with the same peak-to-peak ripple, however the current is now always positive (flowing from input to output, according to our convention.)
Figure 7. Ideal Boost Converter with 25Ω load
But are we still FORCING this circuit to conduct continuously? We'll find out shortly…
Open OL_Boost_concept_actual.asc in LTspice (see Figure 8). This simulation is a close approximation of the ADALM-SR1 configured for this mode.
Figure 8. Open-Loop Boost LTspice Schematic
Note that the simulation includes some of the non-ideal aspects of the real-world circuit:
Note that this schematic still contains many simplifications - the gate driver is not shown, nor are the current sense amplifiers. And since the circuit is powered from an ideal voltage source (zero impedance), input capacitors can be eliminated. This will be a recurring theme, deciding what to simulate and what to assume is close enough to ideal that it can be eliminated from the simulation in the interest of speed, or in some cases, converging at all. The most obvious substitution is the replacement of the top switch with a diode. This will be discussed in more detail shortly, but for now, note that a diode is in fact a switch that conducts when the voltage at the anode is higher than the voltage at the cathode, and does not conduct when the polarity of the voltages are reversed.
BEFORE APPLYING POWER… Configure the ADALM-SR1 board as shown in Figure 9 below:
Figure 9. ADALM-SR1 configuration for Open-Loop Boost, Duty Cycle Control
Set potentiometers to the following approximate settings:
Frequency: 3:00 Duty Cycle: 9:00 Minimum On Time: 7:00 (fully counterclocwise) Current Threshold: 3:00 Voltage Feedback: 12:00
Set potentiometers to the following approximate settings:
Connect a 5V, 1A USB power supply to the Auxiliary Power micro USB jack. At this point, the frequency and duty cycle can be fine-tuned by looking at the D0 signal in Scopy's logic analyzer. Set the frequency to 20kHz (50μs period) and duty cycle to 25% (high time of 12.5μs)
Add Logic Analyzer Plot
Ramp the Power Input to 5V and observe the current sense and switch node waveforms. Note that Scopy's vertical scale can be entered arbitrarily - enter a value of 350mV/Div, which corresponds to 500mA/Div. Figures 10 and 11 show simulated vs. measured results, respectively, at 25% duty cycle. Note that the output voltages match quite well, both are very close to 6V. This is less than the predicted 6.66V of an ideal boost converter, however, note that this circuit starts off with about a 0.4V drop due to to the output diode. Output current is about 240mA (6V/25Ω), which will cause another 275mV drop due to the two 0.1Ω sense resistors and the 0.95Ω resistance of the inductor. This is a total drop of about 0.676V, almost exactly the difference between the ideal case and reality!
Figure 10. Open-Loop Boost Simulation, 20kHz, 25% Duty Cycle, 25Ω Load
Figure 11. Open-Loop Boost Operation, 20kHz, 25% Duty Cycle, 25Ω Load
Next, increase the duty cycle to 50%. Figures 12 and 13 show simulated vs. measured results, respectively, at 50% duty cycle.
Figure 12. Open-Loop Boost Simulation, 20kHz, 50% Duty Cycle, 25Ω Load
Figure 13. Open-Loop Boost Operation, 20kHz, 50% Duty Cycle, 25Ω Load
Try experimenting with the various load resistors and duty cycle potentiometer. The ADALM-SR1 does have a level of protection from stressful operating conditions: load and inductor overheating, output overvoltage, etc., but in this configuration please observe the following precautions:
Describe in more detail why we replaced the top switch with a diode, simulation with an ideal diode, and show that it's equivalent to the synchronous circuit when operating in CCM.
With the circuit still configured as in Activity 2, reduce, or “lighten”, the output load by removing the 50Ω and 100Ω load resistor jumpers, leaving the two 200Ω jumpers in place for a total load resistance of 100Ω. You should notice the switch node and inductor current take on a drastically different shape. Figure X shows the switch node and inductor current at a 25% duty cycle. The output voltage jumps to 7.74V, HIGHER than the 6.67V predicted by the output voltage equation above (even with the drop of the boost diode and the IxR drop of the sense resistors and inductors.)
Figure x. DCM, 20kHz, 50% Duty Cycle, 100Ω Load
Figure X shows the switch node and inductor current at a 50% duty cycle. The output voltage is measured at 11.6V, again, higher than predicted.
Figure x. DCM, 20kHz, 50% Duty Cycle, 100Ω Load
This is a second mode of operation called “Discontinuous Conduction Mode”, and clearly it needs some additional equations to describe the relationship between input voltage, duty cycle, and now, output loading…
(Simulation and ADALM-SR1, no need to separate, buck basics lab handles the ideal case.)
This lab exercise detailed the “power path” for non-synchronous boost and buck converters, illustrating duty-cycle control and peak current control. These circuits would be practical by themselves in a well-controlled environment, where input voltage and output loading conditions are well-known and stable. But real-world applications rarely fall into this category, so it is necessary to add a means of sensing the output voltage and adjusting the operating parameters (duty cycle or peak current) to maintain regulation as conditions change. This will be covered in the next exercises.
Simulations at 99% duty cycle, and why high boost factors are almost never practical in real life.
The amazing LT1995…
The MOSFETs in the LTspice simulations in this exercise are all either directly driven from a pulse voltage source, or by a voltage-controlled voltage source that “level shifts” a ground-referred signal. But what is used in the actual ADALM-SR1 circuit?
Driving the gate of the low-side (boost) MOSFET seems like such a simple job - Ground the gate, and the MOSFET is off. If you measure the resistance from the gate to ground, the resistance is so high that it is likely that your meter will overrange (assuming the board is clean from flux or other contamination.) And the low threshold voltage of the IRF7470 makes it compatible with 5V logic-level signals. But there are subtleties to driving a MOSFET: Even the boost MOSFET can be tricky to drive - as the MOSFET is turning on, the gate-drain capacitance will draw significant current. And if for some reason the gate drive voltage is too low, due to a collapsing housekeeping supply for example, the MOSFET may not be driven fully on, resulting in excessive power dissipation. The high side (buck) MOSFET is much trickier - the ground-referred gate control signal needs to be “level-shifted” and referred to the MOSFET's source, which toggles back and forth between about -0.4V and the input voltage - quite a challenge. For these reasons, LTC7001s were used. The LTC7001 is specifically designed to drive N-channel MOSFETS, addressing all of these issues.
Timing on the Switching Regulator Active Learning Module is generated by an LTC6992-3 pulse-width modulator and variable frequency oscillator. The frequency range is XX to YY, and the PWM duty cycle of the -3 variant extends from zero to 95%, never reaching 100%. This is a great device for generating timing signals for this board because it can be used both as pulse-width modulator and a clock. As a PWM generator, a simple 0-1V control signal to set the duty-cycle to 0-100% (clipped at 95% for the -3). To use the devices as a clock generator, simply set the duty cycle to 50% by setting the MOD pin to 0.5V.
The -3 variant is used for two reasons: First, it limits the maximum boost factor, providing some redundancy to the overvoltage shutdown circuits. Second, the peak-current control circuit is still active in direct-duty-cycle control mode. This circuit requires clock edges in order to reset, and limiting the duty cycle to 95% ensures that edges occur. (A duty cycle of 100% is a signal that is always high, so there are no edges to reset the current limit.)
Another point about the LTC6992 - the “classic” method of generating a PWM signal is to compare a sawtooth or triangular reference ramp to the modulation signal as shown in the circuit below:
Where V2 is the modulation signal. The upper trace shows the PWM output; note that the duty cycle is high when the modulation signal is high, and vice-versa. The LTC6992 is functionally very similar, with the exception that the response is not immediate - the modulation bandwidth is approximately 10kHz, roughly equivalent to placing a 10kHz, 1-pole filter at the output of V2 in the figure above. As long as the loop bandwidth of the switching regulator is significantly lower than 10kHz (a safe assumption in most of our use cases), the impact is minimal.
A slide deck is provided as a companion to this exercise, and can be used to help in presenting this material in classroom, lab setting, or in hands-on workshops.
(Insert slide deck here)
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