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university:courses:tutorials:cmos-dac-chapter [05 Sep 2013 20:06] – [2.11 CONCLUSIONS] Doug Merceruniversity:courses:tutorials:cmos-dac-chapter [21 Jan 2021 16:09] (current) – [2.11 CONCLUSIONS] Doug Mercer
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 Segmented architectures, where the full resolution of the converter is spread across two or more sub-DACs, can be used for both current-and voltage-output DACs. The voltage across the decoded resistor in a resistor string divider circuit can be further subdivided to build a voltage-segmented DAC. This subdivision can be achieved through a second voltage divider circuit or with even a different architecture, as shown in Figure 3. The output of the overall DAC remains monotonic as long as the individual segments are monotonic and the offsets of the two buffer amplifiers in Figure 3 are less than one LSB. Monotonicity is easy to achieve because the individual segments have lower resolution. Segmentation has the added benefit of reducing the number of resistors (or current sources)required to achieve a given resolution, allowing smaller die sizes. Thus, it is common for high-resolution DACs to be segmented. Overall linearity is still determined by the matching of individual elements.  Segmented architectures, where the full resolution of the converter is spread across two or more sub-DACs, can be used for both current-and voltage-output DACs. The voltage across the decoded resistor in a resistor string divider circuit can be further subdivided to build a voltage-segmented DAC. This subdivision can be achieved through a second voltage divider circuit or with even a different architecture, as shown in Figure 3. The output of the overall DAC remains monotonic as long as the individual segments are monotonic and the offsets of the two buffer amplifiers in Figure 3 are less than one LSB. Monotonicity is easy to achieve because the individual segments have lower resolution. Segmentation has the added benefit of reducing the number of resistors (or current sources)required to achieve a given resolution, allowing smaller die sizes. Thus, it is common for high-resolution DACs to be segmented. Overall linearity is still determined by the matching of individual elements. 
  
 +{{ :university:courses:tutorials:figure3.png?620 |}}
 +
 +<WRAP centeralign> Figure 3 Monotonicity is easily achieved because the individual segments have lower resolution. </WRAP>
 ==== 1.4 R-2R LADDER DACS ==== ==== 1.4 R-2R LADDER DACS ====
  
 The R-2R, or ladder, architecture simplifies resistor-matching requirements since only two resistor values are required in a 2:1 ratio. The R-2R architecture can be used as a voltage-or current-mode DAC. Most R-2R current-mode architectures are based on the circuit shown in Figure 4a. An external reference is applied to the Vref pin. The R-2R ladder divides the input current into binary-weighted currents. These currents are steered to node 1 or node 2 depending on the digital input. The current-output node is often connected to an op amp configured as a current-to-voltage converter. For matching reasons, the op-amp feedback resistor is usually included on the DAC chip. The switches are always at ground potential, and their voltage rating does not affect the reference voltage rating. If the switches are designed to carry current in either direction, a variable or ac signal may be used as the reference, resulting in a multiplying DAC. The input impedance of Vref is constant and equal to R. The disadvantages of this architecture include the inversion introduced by the op amp requiring both positive and negative power supplies, and the complicated stabilization of the op amp, as the DAC output impedance, seen at node 1, varies with digital input. Current mode operation also results in higher glitch, since the switches connect directly to the output. Voltage-mode R-2R DACs switch resistors between Vref and ground. The reference voltage is applied to node 1. Each rung on the ladder provides a binary-scaled value with the output taken as the cumulative voltage at the end of the ladder as shown in Figure 4b. The output voltage has constant impedance, simplifying amplifier stabilization. A positive reference voltage will provide a positive output, so single supply operation is possible. Glitch generated by switch capacitance is minimized. The drawback is that the reference input impedance varies widely, so a low-impedance reference must be used. Also, the switches operate from ground to Vref , restricting the allowed range of the reference.  The R-2R, or ladder, architecture simplifies resistor-matching requirements since only two resistor values are required in a 2:1 ratio. The R-2R architecture can be used as a voltage-or current-mode DAC. Most R-2R current-mode architectures are based on the circuit shown in Figure 4a. An external reference is applied to the Vref pin. The R-2R ladder divides the input current into binary-weighted currents. These currents are steered to node 1 or node 2 depending on the digital input. The current-output node is often connected to an op amp configured as a current-to-voltage converter. For matching reasons, the op-amp feedback resistor is usually included on the DAC chip. The switches are always at ground potential, and their voltage rating does not affect the reference voltage rating. If the switches are designed to carry current in either direction, a variable or ac signal may be used as the reference, resulting in a multiplying DAC. The input impedance of Vref is constant and equal to R. The disadvantages of this architecture include the inversion introduced by the op amp requiring both positive and negative power supplies, and the complicated stabilization of the op amp, as the DAC output impedance, seen at node 1, varies with digital input. Current mode operation also results in higher glitch, since the switches connect directly to the output. Voltage-mode R-2R DACs switch resistors between Vref and ground. The reference voltage is applied to node 1. Each rung on the ladder provides a binary-scaled value with the output taken as the cumulative voltage at the end of the ladder as shown in Figure 4b. The output voltage has constant impedance, simplifying amplifier stabilization. A positive reference voltage will provide a positive output, so single supply operation is possible. Glitch generated by switch capacitance is minimized. The drawback is that the reference input impedance varies widely, so a low-impedance reference must be used. Also, the switches operate from ground to Vref , restricting the allowed range of the reference. 
- 
-{{ :university:courses:tutorials:figure3.png?620 |}} 
- 
-<WRAP centeralign> Figure 3 Monotonicity is easily achieved because the individual segments have lower resolution. </WRAP> 
  
 {{ :university:courses:tutorials:figure4.png?620 |}} {{ :university:courses:tutorials:figure4.png?620 |}}
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 A number of major contributors to errors and distortion in modern switched current DACs have been discussed. Static device matching can be addressed either though statistical averaging or calibration. One or more cascodes can be included, along with insuring that the output switches remain in saturation, to reduce the effect of output impedance variation. The importance of gate drive signals was explored. Much like the flash ADC, clock distribution is a key factor. Digital data pattern generated noise needs to be addressed and the effect on clock noise can be a major source of distortion. Return-to-zero switching can be employed to retime the output sampling time. The use of a quad switch and constant data activity switching techniques can shift spurious outputs to the sampling frequency. A number of major contributors to errors and distortion in modern switched current DACs have been discussed. Static device matching can be addressed either though statistical averaging or calibration. One or more cascodes can be included, along with insuring that the output switches remain in saturation, to reduce the effect of output impedance variation. The importance of gate drive signals was explored. Much like the flash ADC, clock distribution is a key factor. Digital data pattern generated noise needs to be addressed and the effect on clock noise can be a major source of distortion. Return-to-zero switching can be employed to retime the output sampling time. The use of a quad switch and constant data activity switching techniques can shift spurious outputs to the sampling frequency.
  
-**Return to [[university:courses:electronics:text:chapter-19|Previous Chapter]]**+**Return to [[adi>/media/en/training-seminars/design-handbooks/Basic-Linear-Design/Chapter6.pdf|Previous Chapter]]**
  
 **Go to [[university:courses:electronics:text:chapter-20|Next Chapter]]** **Go to [[university:courses:electronics:text:chapter-20|Next Chapter]]**
university/courses/tutorials/cmos-dac-chapter.txt · Last modified: 21 Jan 2021 16:09 by Doug Mercer

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