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======Chapter 11: The Current Mirror======

=====11.1 Basic principles=====

A current mirror is a circuit block which functions to produce a copy of the current in one active device by replicating the current in second active device. An important feature of the current mirror is a relatively high output resistance which helps to keep the output current constant regardless of load conditions. Another feature of the current mirror is a relatively low input resistance which helps to keep the input current constant regardless of drive conditions. The current being 'copied' can be, and often is, a varying signal current. Conceptually, an ideal current mirror is simply an ideal current amplifier with a gain of -1. The current mirror is often used to provide bias currents and active loads in amplifier stages.Given a current source as the input, we convert the current (entering the current mirror) into a voltage and then use this voltage to control a current sink (the current exiting the mirror); as a result, we obtain a current sink (figure 11.1a). Conversely, given a current sink as the input, we convert the input current (exiting the current mirror) into a voltage and then use this voltage to control a current source (figure 11.1b); as a result, now we obtain a current source. We can generalize this basic current mirror structure in a first conclusion:

A current mirror consists of a current-to-voltage converter consecutively connected to a voltage-to-current converter.

{{ :university:courses:electronics:text:chptr11-f1.png?500 |}}

<WRAP centeralign > Figure 11.1, Current Mirror (a) Sink (b) Source </WRAP>

It should be noted that the two converters may have a linear relationship (for example where V<sub>OUT</sub> = I<sub>IN</sub>R and I<sub>OUT</sub>= V<sub>IN</sub>/R) like a resistor but this linear relationship is not required. The converters might be non-linear devices having whatever transfer or I to V characteristics that may even depend on another quantity (such as temperature); the only requirement is the characteristics be the inverse of each other. For example, if the I to V converter implements a function v = f(i) and the other represents the inverse function i = f <sup>-1</sup>(v) the whole function is v = f(i) = f(f <sup>-1</sup>(v)) . So, we can formulate the second conclusion: A current mirror consists of two consecutively connected converters that have inverse transfer functions.

=====11.2 An input stage to convert current to voltage=====

We need a configuration where our active element of choice, a transistor, serves as the desired current-to-voltage converter. However, the transistor is a unidirectional device, where for the BJT the base emitter voltage controls the collector current or for the FET the gate source voltage controls the drain current. Producing the opposite where the collector current controls the V<sub>BE</sub> is not possible in the conventional use of the device as a common emitter amplifier. The solution is to incorporate negative feedback. In this case that means making the transistor adjust its base emitter or gate source voltage, V<sub>BE</sub> or V<sub>GS</sub>, so that the collector or drain current is I<sub>IN</sub> = (V<sub>1</sub>-V<sub>BE</sub>)/R. For this purpose, we simply connect the collector to the base or gate to drain. This results in 100% parallel negative feedback (figure 11.2). As a result, with this reversed transistor, the collector current serves as the input quantity while the base-emitter voltage V<sub>BE</sub> serves as the output quantity with a logarithmic transfer function. The input part of the simple BJT current mirror is just a bipolar transistor with 100% parallel negative feedback. Similarly, a diode connected enhancement mode MOS FET (gate tied to drain) will serve as a similar current to voltage converter with V<sub>GS</sub> as the output quantity rather than V<sub>BE</sub>.

{{ :university:courses:electronics:text:chptr11-f2.png?500 |}}

<WRAP centeralign > Figure 11.2, Current to Voltage Converter </WRAP>

=====11.3 An output stage to convert voltage to current=====

A bipolar transistor can be driven by a voltage or by a current. If we consider the base emitter voltage, V<sub>BE</sub>, as the input and the collector current, I<sub>C</sub>, as the output (figure 11.3), we can think of a transistor as a non-linear voltage-to-current converter having an exponential characteristic. The base can be directly driven by the voltage output of the I-to-V converter we just discussed. The collector provides the output terminal of our simple current mirror: The output V to I converter stage of the simple current mirror is just a transistor acting as a non-linear (exponential for BJT) voltage-to-current converter. Again if a MOS transistor were used for the input stage the output stage would be a MOS transistor with the gate serving as the voltage input and the drain as the current output.

{{ :university:courses:electronics:text:chptr11-f3.png?500 |}}

<WRAP centeralign > Figure 11.3, Voltage to Current Converter </WRAP>

=====11.4 Assembling the complete circuit=====

The final step is to connect the output of the input stage (the base emitter junction of Q<sub>1</sub>) to the input of the output stage (the base emitter junction of Q<sub>2</sub>) to build the basic BJT current mirror circuit (figure 11.4). At this point we will concentrate on the issues involved with the BJT current mirror and pick back up with the MOS current mirror in section 11.6.

{{ :university:courses:electronics:text:chptr11-f4.png?500 |}}

<WRAP centeralign > Figure 11.4, BJT Current Mirror </WRAP>

====11.4.1 Mirror Gain other than 1====

If transistors Q<sub>1</sub> and Q<sub>2</sub> in figure 11.4 are identical (that is have the same size emitter and thus equal I<sub>S</sub>) the input current to output current ratio or gain is ideally 1. There are often occasions when a gain other than one is required. When building circuits from discreet devices only simple integer ratios are possible while in microelectronic integrated circuits it is possible to make transistors with arbitrary emitter areas, A. However, even in integrated circuits the best design practice is to use identical unit size transistors when making current mirrors.

{{ :university:courses:electronics:text:chptr11-f5.png?600 |}}

<WRAP centeralign > Figure 11.4.1, Current Mirror with non-unary gain ratio </WRAP>

If on the input side of the mirror we connect N identical devices in parallel and connect M devices in parallel on the output side, the gain of the mirror will be M/N. In figure 11.4.1 we see an example where 2 (N=2) devices are connected together on the input and 3 (M=3) devices are connected together on the output. The mirror gain will thus be 3/2 or 1.5. Since all five transistors share the same V<sub>BE</sub>voltage, their collector currents, I<sub>C</sub>, will all be equal. The input current I<sub>IN</sub> splits equally in Q<sub>1</sub> and Q<sub>2</sub> such that:

<m> I_C = I_IN/2 </m> ,
<m> I_OUT = 3I_C </m> or <m>(3/2)I_IN</m> 

=====11.5 Imperfections of the simple mirror=====

There are three primary error sources that make the simple 2 transistor mirror less than ideal. The first is the mirror gain. Ideally I<sub>OUT</sub> should exactly equal I<sub>IN</sub>. There are systematic and random factors that make this not the case. The second is the incremental output resistance, which determines how much the output current varies with the voltage seen at the mirror output. The third limitation is the minimum voltage drop across the output leg of the mirror necessary to maintain the desired output current. This minimum voltage, called output compliance, is determined by the need to keep the output transistor of the mirror in the active region. There are also a number of secondary performance issues with mirrors, for example, temperature stability and frequency response.

====11.5.1 Gain Errors====

An error source in this simple BJT based current mirror is that the transistors Q<sub>1</sub> and Q<sub>2</sub> (figure 11.4) each remove a base current I<sub>B</sub> from the input current I<sub>IN</sub>. 
As a result, the output current is smaller than the input current:

<m> I_OUT = I_IN - 2I_B </m>

As was already discussed, current mirrors can just as easily be made from MOS FET transistors. The I-to-V and V-to-I functions are different but of course are still the inverse of each other. A significant advantage of the MOS current mirror is the lack of base current induced error that BJT current mirrors suffer. There are methods to correct or compensate for the base current in BJT current mirrors which will be discussed in detail in later sections of this chapter.

====11.5.2 Compliance voltage====

It is necessary to keep the output (BJT) transistor out of saturation, V<sub>CB</sub> = 0 V. Or from another 
perspective, not allow the collector base junction to forward bias. That means the lowest output voltage that 
results in the correct output current, the compliance voltage, is V<sub>OUT</sub> = V<sub>CV</sub> = 
V<sub>BE</sub> under bias conditions with the output transistor at the output current level I<sub>C</sub> and 
with V<sub>CB</sub> = 0 V or, restating the V<sub>BE</sub>relation from earlier:

{{ :university:courses:electronics:text:chptr11-e1.png?150 |}}

Where V<sub>T</sub> is the thermal voltage and I<sub>S</sub> is the reverse saturation current.

====11.5.3 Output resistance====

The V<sub>CB</sub> of Q<sub>1</sub> in the mirror is zero. If V<sub>CB</sub> is greater than zero in the 
output transistor Q<sub>2</sub>, the collector current in Q<sub>2</sub> will be somewhat larger than 
Q<sub>1</sub> due to the Early effect. In other words, the mirror has a finite output resistance given by the 
r<sub>O</sub> of the output transistor, namely:

{{ :university:courses:electronics:text:chptr11-e2.png?200 |}}

Where:\\
V<sub>A</sub> is the Early voltage\\ 
V<sub>CB</sub> is the collector-to-base voltage

As we learned in an earlier chapter, the inclusion of emitter degeneration resistors (R<sub>E1</sub> and 
R<sub>E2</sub> in figure 11.5) can increase the effective collector impedance seen at the mirror output. In 
order for the mirror gain to remain equal to 1, R<sub>E1</sub> must of course equal R<sub>E2</sub>. The added 
voltage drop across the emitter resistor R<sub>E2</sub> (I<sub>OUT</sub> x R<sub>E2</sub>) adds to the 
minimum allowable output voltage (see section 11.5.2).

While resistors could also be added to the sources in an MOS based mirror, it is often more effective to 
simple increase the channel length, L, of the transistors. The longer the channel the less it is affected by 
the channel length modulation due to the increasing drain voltage.

{{ :university:courses:electronics:text:chptr11-f6.png?500 |}}

<WRAP centeralign > Figure 11.5, Emitter degeneration included to boot output resistance. </WRAP>

It is important to note that the inclusion of emitter resistors does not reduce the reduction in the output 
current I<sub>OUT</sub> caused by the finite beta of Q<sub>1</sub> and Q<sub>2</sub>. A compensating voltage 
can be inserted by including resistor R<sub>B</sub>, of the correct value, as shown in figure 11.6.

{{ :university:courses:electronics:text:chptr11-f7.png?600 |}}

<WRAP centeralign > Figure 11.6, Adding a resistor in the base of Q<sub>1</sub> tends to compensate for the finite beta of Q<sub>2</sub> </WRAP>

For V<sub>CB</sub> close to zero (that is, neglecting base-width modulation errors) the necessary value for 
R<sub>B</sub> is:

{{ :university:courses:electronics:text:chptr11-e3.png?300 |}}

For example, using A = 2 ( a mirror gain of 2 ), I<sub>IN</sub> = 1mA, so r<sub>E</sub> = 26Ω and 
R<sub>E1</sub> = 500Ω (introducing about 500mV of degeneration) R<sub>B</sub> should be 1578Ω if β is enough 
larger than A so that factor can be ignored, or 1626Ω if it is included and beta is 100. Clearly, this 
compensation method becomes unpredictable when β is small and is comparable to A and will never be precise 
because β<sub>1</sub> and β<sub>2</sub> are not in general equal. However, this technique can be of practical 
utility in many cases.

=====11.6 Basic MOSFET current mirror=====

The simple current mirror can, obviously, also be implemented using MOSFET transistors, as shown in figure 
11.7. We know that transistor M<sub>1</sub> is operating in the saturation region because V<sub>DS</sub> is 
greater than or equal to V<sub>GS</sub>. Transistor M<sub>2</sub>will also be in saturation so long as the 
output voltage is larger than its saturation voltage. In this simple configuration, the output current 
I<sub>OUT</sub> is directly related to I<sub>IN</sub>.

{{ :university:courses:electronics:text:chptr11-f8.png?600 |}}

<WRAP centeralign > Figure 11.7 Simple MOS current mirror </WRAP>

The drain current of a MOSFET I<sub>D</sub> is a function of both the gate to source voltage and the drain to 
gate voltage of the MOSFET given by I<sub>D</sub> = f (V<sub>GS</sub>, V<sub>DG</sub>), a relationship 
derived from the functionality of the MOSFET device. In the case of transistor M<sub>1</sub> of the mirror, 
I<sub>D</sub> = I<sub>IN</sub>. Input current I<sub>IN</sub> is a known current, and can be provided by a 
resistor as shown in the figure, or by a threshold-referenced or self-biased current source to ensure that it 
is constant, independent of voltage supply variations.

Using V<sub>DG</sub>=0 for transistor M<sub>1</sub>, the drain current in M<sub>1</sub> is I<sub>D</sub> = f 
(V<sub>GS</sub>,V<sub>DG</sub>=0), so we find: f (V<sub>GS</sub>, 0) = I<sub>IN</sub>, implicitly determining 
the value of V<sub>GS</sub>. Thus I<sub>IN</sub> sets the value of V<sub>GS</sub>. The circuit in the diagram 
forces the same V<sub>GS</sub> to apply to transistor M<sub>2</sub>. If M<sub>2</sub> also is biased with 
zero V<sub>DG</sub> and provided transistors M<sub>1</sub> and M<sub>2</sub> have good matching of their 
properties, such as channel length, width, threshold voltage etc., the relationship I<sub>OUT</sub> = f 
(V<sub>GS</sub>,V<sub>DG</sub>=0 ) applies, thus setting I<sub>OUT</sub> = I<sub>IN</sub>; that is, the 
output current is the same as the input current when V<sub>DG</sub>=0 for the output transistor, and both 
transistors are matched.

The drain-to-source voltage can be expressed as V<sub>DS</sub>=V<sub>DG</sub> + V<sub>GS</sub>. With this 
substitution, the Shichman-Hodges model provides an approximate form for function f(V<sub>GS</sub>,V<sub>DG</sub>):

<m> I_D = f(V_GS,V_DG ) = 1/2 K_p (W/L) (V_GS-V_th )^2 (1+λV_DS ) </m>

<m> I_D  = 1/2 K_p (W/L) (V_GS-V_th )^2 (1+λ(V_DG+V_GS )) </m>

Where:\\
Kp is a technology related constant associated with the transistor,\\
W/L is the width to length ratio of the transistor,\\
V<sub>GS</sub> is the gate-source voltage, V<sub>th</sub> is the threshold voltage, V<sub>DS</sub> is the 
drain-source voltage\\
λ is the channel length modulation constant\\
 
**Output resistance**

Because of channel-length modulation, the mirror has a finite output resistance given by the //ro// of the 
output transistor, namely:

{{ :university:courses:electronics:text:chptr11-e04.png?200 |}}

Where:\\
λ = channel-length modulation parameter\\
V<sub>DS</sub> = drain-to-source bias.

**Compliance voltage**

To keep the output transistor resistance high, V<sub>DG</sub> = 0 V. That means the lowest output voltage 
that  results in correct mirror behavior, the compliance voltage, is V<sub>OUT</sub> = V<sub>CV</sub> = 
V<sub>GS</sub> for the output  transistor at the output current level with V<sub>DG</sub> = 0 V, or using the 
inverse of the f- function, f<sup>-1</sup>:

{{ :university:courses:electronics:text:chptr11-e6.png?500 |}}

For the Shichman-Hodges model, f<sup>-1</sup> is approximately a square-root function.

=====11.7 Improved current mirrors=====

====11.7.1 Buffered Feedback current mirror====

Figure 11.8 shows a mirror where the simple wire connecting the collector of Q<sub>1</sub> to its base is replaced by an emitter follower buffer. This improvement to the simple current mirror is referred to as an emitter follower augmented mirror. The current gain (ß<sub>Q3</sub>) of the emitter follower buffer stage (Q<sub>3</sub>) greatly reduces the gain error caused by the finite base currents of Q<sub>1</sub> and Q<sub>2</sub>.

{{ :university:courses:electronics:text:chptr11-f9.png?500 |}}

<WRAP centeralign > Figure 11.8 Buffered Feedback current mirror. </WRAP>

One thing to note that is different in this mirror configuration vs. the simple two transistor mirror is that 
the Collector-Base voltage, V<sub>CB</sub>, of Q<sub>1</sub> is no longer zero. It is equal to the 
V<sub>BE</sub> of Q<sub>3</sub>. Given the effect of the finite output resistance (Early effect ) the output 
current I<sub>OUT</sub> in Q<sub>2</sub> will most closely match I<sub>IN</sub> when the collector voltage of 
Q<sub>2</sub> is the same as that of Q<sub>1</sub> which is 2XV<sub>BE</sub> above the common voltage. Also 
note that when driven by a resistor, like R<sub>1</sub>, I<sub>IN</sub> will now be 
(V<sub>1</sub>-V<sub>BE1</sub>-V<sub>BE2</sub>)/R<sub>1</sub>.

Another consequence of adding the emitter follower buffer is, in general, a loss in the frequency response of 
the mirror. Transistor Q<sub>3</sub> is potentially operating at a very small current of 2I<sub>B</sub>. If 
there were to be a significant capacitance to ground at the base connection common to Q<sub>1</sub> and 
Q<sub>2</sub> the current available to discharge this current will also be small equal to 2I<sub>B</sub>. But 
the current available to charge this node is potentially equal to ß<sub>Q3</sub>I<sub>IN</sub> which is very 
much larger than 2I<sub>B</sub>. This asymmetry in the charging vs. discharging current available for this 
node in the current mirror can lead to very undesirable response to fast changes to I<sub>IN</sub>.

====11.7.2 The Wilson current mirror====

A Wilson current mirror or Wilson current source, named after George Wilson, is an improved mirror circuit 
configuration designed to provide a more constant current source or sink. It provides a much more accurate 
input to output current gain. The structure is shown in figure 11.9.

{{ :university:courses:electronics:text:chptr11-f10.png?500 |}}

<WRAP centeralign > Figure 11.9 The Wilson Current Mirror </WRAP>

We will be making the following two assumptions. First, all transistors have the same current gain ß. Second, 
Q<sub>1</sub> and Q<sub>2</sub>are matched, so their collector currents are equal. Therefore, I<sub>C1</sub> 
= I<sub>C2</sub> (= I<sub>C</sub>) and I<sub>B1</sub> = I<sub>B2</sub> (= I<sub>B</sub>) .

The base current of Q<sub>3</sub> is given by,

{{ :university:courses:electronics:text:chptr11-e7.png?150 |}}

The emitter of Q<sub>3</sub> current by,

{{ :university:courses:electronics:text:chptr11-e8.png?200 |}}

Looking at figure 11.9, it can be seen that <sub>IE3</sub> = I<sub>C2</sub> + I<sub>B1</sub> + I<sub>B2</sub> 
Substituting for I<sub>C2</sub>, I<sub>B1</sub> and I<sub>B2</sub>, I<sub>E3</sub> = I<sub>C</sub> + 2I<sub>B</sub> 

so,

{{ :university:courses:electronics:text:chptr11-e9.png?200 |}}

Substituting for I<sub>E3</sub>
 
{{ :university:courses:electronics:text:chptr11-e10.png?250 |}}

rearranging,

{{ :university:courses:electronics:text:chptr11-e11.png?200 |}}

The current through R<sub>1</sub> is given by, I<sub>R1</sub> = I<sub>C1</sub> + I<sub>B3</sub> 

But, I<sub>C1</sub> = I<sub>C2</sub> = I<sub>C</sub>

Substituting for I<sub>C</sub> and since 
{{:university:courses:electronics:text:chptr11-e7.png?100|}}
we get,

{{ :university:courses:electronics:text:chptr11-e12.png?250 |}}

Therefore,

{{ :university:courses:electronics:text:chptr11-e13.png?250 |}}

And finally,

{{ :university:courses:electronics:text:chptr11-e14.png?200 |}}

From the above equation we can see that if

{{ :university:courses:electronics:text:chptr11-e15.png?300 |}}

And the output current (assuming the base-emitter voltage of all transistors to be 0.7 V) is calculated as,

{{ :university:courses:electronics:text:chptr11-e16.png?300 |}}

Note that the output current is equal to the input current I<sub>R1</sub> which in turn is dependent on 
V<sub>1</sub> and R<sub>1</sub>. If V<sub>1</sub> is not stable, the output current will not be stable. Thus 
the circuit does not act as a regulated constant current source.

In order for it to work as a constant current source, R<sub>1</sub> must be replaced with a constant current 
source.

**Advantages over other configurations**

This circuit has the advantage of virtually eliminating the base current mismatch of the conventional BJT 
current mirror thereby ensuring that the output current I<sub>C3</sub> is almost equal to the reference or 
input current I<sub>R1</sub>. It also has a very high output impedance due to the negative feedback through 
Q<sub>1</sub> back to the base of Q<sub>3</sub>.

====11.7.3 Further improvement (full Wilson Mirror)====

Adding a fourth transistor to the simple Wilson current mirror in figure 11.10, we have the modified or 
improved Wilson mirror.  The improved input to output current accuracy is accomplished by equalizing the 
collector voltages of Q<sub>1</sub> and Q<sub>2</sub> at 1 V<sub>BE</sub>. This leaves the finite ß and 
voltage differences of each of Q<sub>1</sub> and Q<sub>2</sub> as the remaining unbalancing influences in the 
mirror.

{{ :university:courses:electronics:text:chptr11-f11.png?500 |}}

<WRAP centeralign > Figure 11.10 The improved Wilson Current Mirror </WRAP>

=====11.8 Widlar current source=====

A Widlar current source is a modification of the basic two-transistor current mirror that incorporates an 
emitter degeneration resistor for only the output transistor, enabling the current source to generate low 
currents using only moderate resistor values. This circuit is named for its inventor, Robert Widlar, and was 
patented in 1967.

The Widlar circuit may be used with bipolar transistors or MOS transistors. An example application is in the 
now famous uA741 operational amplifier, and Widlar used the circuit in many of his designs.

====11.8.1 Analysis====

{{ :university:courses:electronics:text:chptr11-f12.png?550 |}}

<WRAP centeralign > Figure 11.11 A version of the Widlar current source using bipolar transistors. </WRAP>

Figure 11.11 is an example Widlar current source using bipolar transistors, where the emitter resistor 
R<sub>2</sub> is connected in series with the emitter of output transistor Q<sub>2</sub>, and has the effect 
of reducing the current in Q<sub>2</sub> relative to Q<sub>1</sub>. The key to this circuit is that the 
voltage drop across the resistor R<sub>2</sub> subtracts from the base-emitter voltage of transistor 
Q<sub>2</sub>, thereby reducing the collector current compared to transistor Q<sub>1</sub>. A simulation plot 
showing this reduction in I<sub>C2</sub> is presented in figure 11.12.

{{ :university:courses:electronics:text:chptr11-f13.png?550 |}}

<WRAP centeralign > Figure 11.12 Plot of the collector current of Q<sub>1</sub> and Q<sub>2</sub> 
R<sub>1</sub> = 15KΩ, R<sub>2</sub> = 300  </WRAP>

This observation is expressed by using KVL around the base emitter loop of the circuit in Figure 11.11 as:

{{ :university:courses:electronics:text:chptr11-e17.png?400 |}}

Where ß<sub>2</sub> is the beta of the output transistor, which may not be the same as that of the input 
transistor, in part because the currents in the two transistors are very different. The variable 
I<sub>B2</sub> is the base current of the output transistor, V<sub>BE</sub> refers to base-emitter voltage.  
If we neglect the effect of finite ß and use the V<sub>BE</sub> equation we can obtain a useful formula for 
the output current:

{{ :university:courses:electronics:text:chptr11-e18.png?220 |}}

where V<sub>T</sub> is the thermal voltage, I<sub>IN</sub> = I<sub>C1</sub> and I<sub>OUT</sub> = I<sub>C2</sub>.

Suppose we want to create a 100uA output current from a 300uA input current as in the simulation plot of 
figure 11.12. V<sub>T</sub> is 26mV times ln(3) is 28.5mV. 28.5mV divided by 100uA is 285 ohms. 
This equation makes the approximation that the currents are both much larger than the saturation currents 
I<sub>S1</sub>, I<sub>S2</sub>, an approximation valid except for very low current levels. In the following 
the distinction between the two scale currents is dropped, although the difference can be important, for 
example, if the two transistors are designed with different emitter areas.

====11.8.2 Output impedance====

{{ :university:courses:electronics:text:chptr11-f14.png?500 |}}

<WRAP centeralign > Figure 11.13 Small-signal circuit for finding output resistance of the Widlar source  
shown in figure 11.11. </WRAP>

A test current I/<sub>x</sub> is applied at the output, and the output resistance is then R<sub>O</sub> = 
V<sub>x</sub> / I<sub>x</sub>.

An important property of a current source is its small signal incremental output impedance, which should 
ideally be infinite. The emitter degeneration resistance introduces local current feedback for transistor 
Q<sub>2</sub>. Any increase in the current in Q<sub>2</sub> increases the voltage drop across R<sub>2</sub>, 
reducing the V<sub>BE</sub> for Q<sub>2</sub>, thereby countering the increase in current. This feedback 
means the output impedance of the circuit is increased, because the feedback involving R<sub>2</sub> forces 
use of a larger voltage to drive a given current.

Output resistance is found using a small-signal model for the circuit, shown in Figure 11.13. The transistor 
Q<sub>1</sub> is replaced by its small-signal emitter resistance r<sub>E</sub> because it is diode connected. 
In a diode-connected transistor the collector is short-circuited to the base, so the transistor 
collector-base junction has no time-varying voltage across it. As a result, the transistor behaves like the 
base-emitter diode, which at low frequencies has a small-signal circuit that is simply the resistor 
r<sub>E</sub> = V<sub>T</sub> / I<sub>E</sub>, with I<sub>E</sub> the DC Q-point emitter current. The 
transistor Q<sub>2</sub> is replaced with its hybrid-pi model. A test current I<sub>x</sub> is attached at 
the output.

Using the figure, the output resistance is determined using Kirchhoff's laws. Using Kirchhoff's voltage law 
from the ground on the left to the ground connection of R<sub>2</sub>:

{{ :university:courses:electronics:text:chptr11-e19.png?300 |}}

Rearranging:

{{ :university:courses:electronics:text:chptr11-e20.png?300 |}}

Using Kirchhoff's voltage law from the ground connection of R<sub>2</sub> to the ground of the test current:

{{ :university:courses:electronics:text:chptr11-e21.png?300 |}}

or, substituting for I<sub>b</sub>:

Eq. 4

{{:university:courses:electronics:text:chptr11-e22.png?340|}}{{:university:courses:electronics:text:chptr11-e23.png?260|}}


According to Eq. 4, the output resistance of the Widlar current source is increased over that of the output 
transistor itself (which is r<sub>O</sub>) so long as R<sub>2</sub> is large enough compared to the 
r<sub>p</sub> of the output transistor. (Large resistances R<sub>2</sub> make the factor multiplying 
r<sub>O</sub> approach the value (ß +1).) The output transistor carries a low current, making r<sub>p</sub> 
large, and increase in R<sub>2</sub> tends to reduce this current further, causing a correlated increase in 
r<sub>p</sub>. Therefore, a goal of R<sub>2</sub> >> r<sub>p</sub> can be unrealistic, and further discussion 
is provided below. The resistance R<sub>1</sub> / r<sub>E</sub> usually is small because the emitter 
resistance r<sub>E</sub> usually is only a few ohms.

** BJT Current Mirror [[university:courses:electronics:electronics-lab-6|Lab Activity]] **\\
** MOS Current Mirror [[university:courses:electronics:electronics-lab-6m|Lab Activity]] **

=====11.9. The Zero Gain Amplifier=====

When designing a circuit it is important to take into account the wide variation in certain device values 
from one to another. A central objective of the designer is to desensitize the circuit to these variations to 
produce a circuit which meets the specifications across all possible conditions. One aspect of design which 
is common to nearly all circuits is the establishment of stable bias or operating point levels. This 
seemingly minor portion of a design can provide the most challenging and interesting circuit problems. Many 
bias generators are centered around the generation of currents to operate the core of the circuit. Current 
generated from simple resistors and diodes or diode connected transistors connected across the power supply 
will vary approximately proportional to the variation of the supply voltage. This variation in the resulting 
bias current is frequently undesirable.

This is to introduce another kind of current mirror, actually a stabilized current source, which has an 
output which had been desensitized to variation in input current. To understand this configuration, it is 
helpful to examine the behavior of a zero gain amplifier. A NMOS version is shown in figure 11.14 but PMOS, 
NPN or PNP transistors will just as well function in this configuration

{{ :university:courses:electronics:text:chptr11-f15.png?550 |}}

<WRAP centeralign > Figure 11.14 NMOS Zero Gain Amplifier </WRAP>

Remembering back to the previous explanation of the common emitter/source amplifier (figure 11.14(a)), the 
gain is a function of the drain (or collector) current and the load resistor. For a given drain current, if 
the drain resistor R<sub>L</sub> is set equal to r<sub>s</sub> then the gain A will be minus 1. 

Alternatively. if the gate is held fixed at the same DC bias level which produces an identical drain current 
as in (a) and an input signal is applied to the top of load resistor R<sub>L</sub> (figure 11.14(b)), then 
the gain will be plus 1. That is if the drain/source output impedance of the transistor is neglected. If we 
now connect the gate to the top of resistor R<sub>L</sub> as in figure 11.14(c), the net gain superimposing 
both paths will be 1 - 1 = 0.

In figure 11.15 we have an NPN transistor biased into conduction with a collector voltage V<sub>C</sub> which 
is less than the base voltage V<sub>BE</sub> by the thermal voltage V<sub>T</sub>= kT/q, (equal to Ic times 
R<sub>L</sub>) and is essentially constant with input voltage changes applied from V<sub>IN</sub>. The 
voltages seen at V<sub>BE</sub> and V<sub>C</sub> are plotted vs. the applied voltage at V<sub>IN</sub> in 
figure 11.14. As we can see while V<sub>BE</sub> continues to rise, V<sub>C</sub> remains much more constant 
and actually decreases above a certain level of V<sub>IN</sub>.

{{ :university:courses:electronics:text:chptr11-f16.png?500 |}}

<WRAP centeralign > Figure 11.15 NPN Zero Gain Amplifier </WRAP>

{{ :university:courses:electronics:text:chptr11-f17.png?500 |}}

<WRAP centeralign > Figure 11.16 Plot of V<sub>BE</sub> and V<sub>C</sub> vs V<sub>IN</sub> for R1 = 10KΩ and 
R<sub>L</sub>=75Ω </WRAP>

A zero gain amplifier made using an enhancement mode NMOS 2N7000 transistor was simulated where the small 
signal AC gain and phase was calculated as the drain current was swept. As can be seen in figure 11.17 there 
is a sharp null or dip in the gain curve at around 345uA. This also occurs at the point where the phase makes 
a sharp transition from 0 degrees to 180 degrees.

{{ :university:courses:electronics:text:chptr11-f18.png?500 |}}

<WRAP centeralign > Figure 11.17 Small signal gain/phase plot of zero gain amplifier vs. I<sub>D</sub> </WRAP>

** BJT Zero Gain Amplifier [[university:courses:electronics:electronics-lab-7|Lab Activity]] **\\
** NMOS Zero Gain Amplifier [[university:courses:electronics:electronics-lab-7m|Lab Activity]] **


=====11.10 Stabilized Current Source=====

Now that we understand the concept of the zero gain amplifier, the objective is to investigate its use to 
produce an output current which is stabilized (less sensitive) to variations of the input current level. This 
current source configuration, figure 11.17, is also sometimes called a Peaking Current Source or 
g<sub>m</sub>-compensated mirror. Because the collector voltage V<sub>C</sub> of transistor Q<sub>1</sub> is 
now more constant with changes in the input supply voltage as represented by V<sub>IN</sub>, it can be used 
as the base voltage of Q<sub>2</sub> to produce a much more constant collector current in transistor 
Q<sub>2</sub>.

{{ :university:courses:electronics:text:chptr11-f19.png?600 |}}

<WRAP centeralign > Figure 11.18 Stabilized (Peaking) current source (g<sub>m</sub>-compensated mirror) </WRAP>

{{ :university:courses:electronics:text:chptr11-f20.png?500 |}}

<WRAP centeralign > Figure 11.19 Plot of the collector current of Q<sub>1</sub> and Q<sub>2</sub> 
R<sub>1</sub> = R<sub>2</sub> = 10KΩ, R<sub>L</sub> = 75Ω </WRAP>

{{ :university:courses:electronics:text:chptr11-f21.png?500 |}}

<WRAP centeralign > Figure 11.20 PTAT current plot of Peaking Current Source </WRAP>

{{ :university:courses:electronics:text:chptr11-f22.png?600 |}}

<WRAP centeralign > Figure 11.21 A combination of the Widlar mirror and peaking current source provides 
further improvement in the regulation of a variable input current. </WRAP>

{{ :university:courses:electronics:text:chptr11-f23.png?500 |}}

<WRAP centeralign > Figure 11.22 Simulation of circuit in figures 11.18 and 11.21 with R<sub>1</sub> = 20KΩ, 
R<sub>L</sub>= 250Ω and R<sub>2</sub>= 1.2KΩ </WRAP>

{{ :university:courses:electronics:text:chptr11-f24.png?500 |}}

<WRAP centeralign > Figure 11.23 cascade of NPN and PNP peaking current sources </WRAP>

** BJT Stabilized current source [[university:courses:electronics:electronics-lab-8|Lab Activity]] **\\
** MOS Stabilized current source [[university:courses:electronics:electronics-lab-8m|Lab Activity]] **

----

**Return to [[university:courses:electronics:text:chapter-10|Previous Chapter]]**

**Go to [[university:courses:electronics:text:chapter-12|Next Chapter]]**

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