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university:courses:electronics:m2k-uart-debug [26 Mar 2019 16:50] – Antoniu Miclaus | university:courses:electronics:m2k-uart-debug [03 Jan 2021 22:21] (current) – fix links Robin Getz | ||
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The objective of this tutorial is to use the Pattern Generator and Logic Analyzer instruments provided by the [[adi> | The objective of this tutorial is to use the Pattern Generator and Logic Analyzer instruments provided by the [[adi> | ||
- | As an example we will use as second device the [[adi> | + | The [[adi> |
===== Background ==== | ===== Background ==== | ||
- | Universal Asynchronous Receiver/ | + | A Universal Asynchronous Receiver/ |
- | The UART transmit | + | The UART transmitter |
<WRAP centeralign> | <WRAP centeralign> | ||
<WRAP centeralign> | <WRAP centeralign> | ||
- | UART transmits data asynchronously, | + | A UART transmits data asynchronously, |
{{: | {{: | ||
<WRAP centeralign> | <WRAP centeralign> | ||
- | When the UART receive | + | When the UART receiver |
- | UART transmitted | + | UART data is organized into bytes. Each byte contains 1 start bit, 5 to 9 data bits (depending on the UART), an optional parity bit, and 1 or 2 stop bits. |
<WRAP centeralign> | <WRAP centeralign> | ||
- | <WRAP centeralign> | + | <WRAP centeralign> |
- | The UART data transmission line is normally held at a high voltage level when no transmission is occurring. To start the transfer of data, the the transmission line is pulled from high to low. When the receiving UART detects the high to low voltage transition, it begins reading the bits in the data frame at the frequency of the baud rate. | + | The UART data transmission line is normally held at a high voltage level when no transmission is occurring. To start the transfer of data, the the transmission line is pulled from high to low. When the receiving UART detects the high to low voltage transition, it interprets this event as as start bit and begins reading |
- | Parity describes the evenness or oddness of a number. The parity bit is a way for the receiving UART to tell if any data has changed during transmission. Bits can be changed by mismatched baud rates, long distance data transfers, etc. After the receiving UART reads the data frame, it counts the number of bits with a value of 1 and checks if the total is an even or odd number. If the parity bit is a 0 (even parity), the 1 bits in the data frame should total to an even number. If the parity bit is a 1 (odd parity), the 1 bits in the data frame should total to an odd number. When the parity bit matches the data, the UART knows that the transmission was free of errors. | + | A parity bit may be included after the data bits. Parity describes |
- | To signal the end of the data packet, the sending UART drives the data transmission line from a low voltage to a high voltage for at least two bit durations. | + | Even parity: for a given set of bits, the occurrences of bits whose value is 1 is counted. If that count is odd, the parity bit value is set to 1. If the count of 1s in a given set of bits is already even, the parity bit value is 0. |
+ | |||
+ | Odd parity: for a given set of bits, if the count of bits with a value of 1 is even, the parity bit value is set to 1 . If the count of bits with a value of 1 is odd, the count is already odd so the parity bit value is 0. | ||
+ | |||
+ | The parity bit is simple error detection scheme, and will detect all single-bit errors. Bits can be changed during transmission by mismatched baud rates, noise picked up on long distance data transfers, etc. Like baud rate, both transmitter and receiver must be set to the same parity configuration. | ||
+ | |||
+ | To signal the end of the data byte, the sending UART drives the data transmission line from a low voltage to a high voltage for at least two bit periods. | ||
===== Hardware Configuration ==== | ===== Hardware Configuration ==== | ||
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* Pin7 - DIO1 | * Pin7 - DIO1 | ||
* Pin8 - DIO0 | * Pin8 - DIO0 | ||
+ | |||
+ | **EVAL-ADICUP3029 UART switch configuration: | ||
+ | |||
+ | * Set S2 to the CENTER position. | ||
+ | |||
+ | (S2 selects which device to connect the ADuCM3029' | ||
+ | |||
+ | ===== Software Configuration ==== | ||
+ | |||
+ | There are several options for which software to use for this demonstration; | ||
+ | |||
+ | [[https:// | ||
+ | |||
+ | |||
===== Scopy Pattern Generator Configuration ==== | ===== Scopy Pattern Generator Configuration ==== | ||
- | First, | + | First, |
The EVAL-ADICUP3029 software application has the UART configured as follows: | The EVAL-ADICUP3029 software application has the UART configured as follows: | ||
Line 89: | Line 109: | ||
===== Scopy Logic Analyzer Configuration ==== | ===== Scopy Logic Analyzer Configuration ==== | ||
- | Several | + | Several |
* Baud rate: 115200 | * Baud rate: 115200 | ||
* Data bits: 8 | * Data bits: 8 | ||
Line 109: | Line 129: | ||
<WRAP centeralign> | <WRAP centeralign> | ||
- | The Logic Analyzer must be set up to “catch” the UART packet | + | The Logic Analyzer must be set up to “catch” the UART byte transfer on the Logic Analyzer plot. Since the UART transfer starts |
<WRAP centeralign> | <WRAP centeralign> | ||
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The Logic Analyzer will wait for the falling edge of the Rx signal to be triggered (corresponding to the start bit). | The Logic Analyzer will wait for the falling edge of the Rx signal to be triggered (corresponding to the start bit). | ||
- | Run a single sweep on the Pattern Generator to send the first UART packet. | + | Run a single sweep on the Pattern Generator to send the first UART byte. |
The result captured by the Logic Analyzer is presented in Figure 10. | The result captured by the Logic Analyzer is presented in Figure 10. | ||
<WRAP centeralign> | <WRAP centeralign> | ||
- | <WRAP centeralign> | + | <WRAP centeralign> |
Analyzing the plot, the byte (ASCII code) corresponding to character " | Analyzing the plot, the byte (ASCII code) corresponding to character " | ||
+ | The decoders available in Scopy allow visualization of the data bytes in ASCII format, including the Start Bit (denoted with " | ||
+ | |||
+ | Now, let's try sending multiple characters and see what happens with our application. | ||
+ | |||
+ | In the Pattern Generator instrument, under the "Data to Send" label, set the data bytes to " | ||
+ | |||
+ | <WRAP centeralign> | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | On the Logic Analyzer, adjust the Time Base and Trigger Position accordingly to be able to see all of the transactions. (i.e. Time Base: 100us and Trigger Position: 300us) | ||
+ | |||
+ | Run Single sweep in The Logic Analyzer and then in the Pattern Generator. | ||
+ | |||
+ | The result captured by the Logic Analyzer is shown in Figure 12. | ||
+ | |||
+ | <WRAP centeralign> | ||
+ | <WRAP centeralign> | ||
+ | |||
+ | The EVAL-ADICUP3029 example program echoes received data bytes as they come in. As expected all the data bytes were received by the EVAL-ADICUP3029 board and sent back on Tx pin. | ||
+ | |||
+ | =====Conclusion===== | ||
+ | |||
+ | In addition to UART, the application includes a set of decoders covering a large number of communication protocols such as I2C, I2S, SPI, JTAG, and others, making ADALM2000 a powerful tool for analyzing and debugging digital signals. | ||
+ | |||
+ | ====Further Reading: | ||
+ | * [[adi> | ||
+ | * [[adi> | ||
+ | * [[resources: | ||
+ | * [[resources: | ||
+ | * [[university: | ||
+ | * [[university: | ||