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Activity: Voltage Level Shifting

Objective:

The objective of this lab activity is to explore circuits that increase the voltage swing or shift the high and/or low logic level of digital signals.

Background:

There are often many cases in digital systems where two or more sections of the system operate from different power supply voltages. When digital signals cross the boundary between these different power supply regions or domains it is necessary to insert a circuit block that translates or shifts the logic levels from the level supplied by one domain for example with a +5 Volt power supply to a second domain with a +9 Volt power supply or a +/- 5 Volt dual supply. One important application example is controlling analog switches where the signals involved are bipolar in nature and require dual ( +/- 5 Volt ) supplies. Such logic level shifting circuits can take many forms. We will be exploring a few examples in this activity.

The simplest form of a voltage level shifter as shown in figure 1(a), uses a pass NMOS device and a pull up resistor ( pull down for PMOS configuration figure 1(b) ). If VIN at the input of the inverter is at a logic high its output goes to ground turning on enhancement mode device MN1 and drives VOUT to ground. Conversely if VIN is at a logic low the inverter output goes to VDDI. With the gate of MN1 also at VDDI it will now be off which allows VOUT to be pulled up to VDDO by resistor R1. Similarly for the negative level shifter in figure 1(b) if VIN is at a logic low the inverter output goes to VDDI turning on enhancement mode device MP1 and drives VOUT to VDDI. With VIN is at a logic high the inverter output goes to ground. With the gate of MP1 also at ground it will now be off which allows VOUT to be pulled down to the negative voltage, VDDO by resistor R1.

Figure 1 Positive (a) and Negative (b) voltage level shift

The strength of the inverter devices, the on resistance of the pass FET, and the parasitic capacitance of the signal lines mainly determine the fall time of the output signal. Also, the rise time of the output signal is determined mostly by the value of the pull-up resistor on the output and the signal-line parasitic capacitance assuming the pass FET turns off instantaneously, which is not generally the case but we assume it is for this discussion. An annoying aspect of resistor loaded level shifters such as this is the DC current that flows in resistor R1. For the positive shifter (a) a current equal to VDDO/R1 flows when VOUT is low. For the negative shifter (b) a current equal to VDDI-VDDO/R1 flows when VOUT is high. As was just pointed out the transition time for the output is a function of R1 and any parasitic capacitance and there will be a trade-off between power dissipation and speed which will determine the optimal value.

We can solve the DC current problem if we can replace the pull up load resistor R1 with a transistor which can be turned on or off as needed. A second voltage level shifter using two complementary drivers and cross-coupled PMOS loads is shown in figure 2. The operation of circuit is as follows. When the input signal VIN is in a logic low state ( at ground ) and with VINB at VDDI because of the first inverter, MN1 turns on ( MN4 is off because of the second inverter ). This pulls the VOUTB signal to ground. This transition of VOUTB turns on MP4 which pulls up the VOUT node to the VDDO voltage rail which turns off MP3. In the opposite case when VIN is at the VDDI rail ( VINB is at ground ), MN1 is off and MN4 is on, which turns on MP3. MP3 pulls up VOUTB to the VDDO rail which turns off MP4. This design ensures that there is never a steady-state DC current path from VDDI or VDDO to ground, which insures very low quiescent current consumption. One design consideration is to size MP3 and MP4 to be weaker than MN1 and MN4 to reduce the potentially large current spikes when the circuit changes state.

Figure 2 Level shifter with low quiescent current

For example, applications for low voltage to high voltage translation are Thin Film Transistor-Liquid Crystal Display panels and piezoelectric motor drivers.

Materials:

ADALM2000 Active Learning Module
Solder-less breadboard and Jumper wires
1 - 9 Volt battery with snap connector
2 Each 10KΩ, 4.7KΩ and 1KΩ resistors
1 - CMOS Hex Inverter, 74HC004 or CD4069
1 - CD4007 CMOS complementary pair array
2 - NMOS transistors (ZVN2110A)
2 - PMOS transistors (ZVP2110A)

Directions:

Build the circuit shown in figure 3 on your solder-less breadboard. Use AWG1 to drive VIN and use the positive power supply, Vp from the ADALM2000 board for VDDI. A 9 Volt battery supplies VDDO. Scope channels 1 and 2 will be used to view the output waveforms.

There are two versions of a positive level shifter circuit using pull-up resistors. The first version using INV1 to drive the source of MN1 with the gate of MN1 connected to the +5V supply rail produces a 0 to +9V swing inverted version of VIN at VOUT1. The second, simple open-drain, version using INV3 to drive the gate of MN2 with the source of MN2 connected to ground produces a 0 to +9V swing non-inverted version of the signal at the input of INV3 at VOUT2. INV2 is inserted between VIN and the input of INV3 so that VOUT1 and VOUT2 both have the same overall inverted phase relationship to VIN.

Figure 3 Two versions of a positive level shifter

Hardware Setup:

Configure AWG channel 1 as a square wave with a 2.5V offset and a 5V amplitude (0 to 5V swing). Set the frequency to 20KHz.

Procedure:

With Scope channel 1 connected to VOUT1 and Scope channel 2 connected to VOUT2 observe the rising and falling edges of the waveform. Replace 10K? resistors R1 and R2 with 4.7KΩ and 1KΩ resistors and compare the relative rise and fall times for each value.

Questions:

Are there any differences in delay or rise/fall times between the two versions of the level shifter? If so why?

Directions:

Build the circuit shown in figure 4 on your solder-less breadboard. Use AWG1 to drive VIN and use the positive power supply, Vp from the ADALM2000 board for VDDI. A 9 Volt battery supplies VDDO. Scope channel 1 can be used to display VIN and channel 2 will be used to view the VOUT waveform. You can also observe the complementary output at the drain ( pin 13 ) of MP1. Pin 7 of the CD4007 needs to be connected to ground and the rest of the unused pins should be connected to VDDO.

Figure 4 Voltage level shifter with PMOS pull-up loads

The ADG3123 is an 8-channel, non-inverting CMOS to high voltage level translator.

Questions:

How does the delay or rise/fall times for the level shifters in figure 3 compare to the level shifter in figure 4? Explain why?

For Further Reading:

http://en.wikipedia.org/wiki/Logic_level
http://www.analog.com/static/imported-files/tutorials/MT-098.pdf

Return to Lab Activity Table of Contents.

Appendix: Making an inverter with the CD4007 transistor array

Below is the schematic and pinout for the CD4007:

CD4007 CMOS transistor array pinout

As many as three individual inverters can be built from one CD4007 package. The simplest first one to configure as shown below is by connecting pins 8 and 13 together as the inverter output. Pin 6 will be the input. Be sure to connect pin 14 VDD to power and pin 7 VSS to ground.

The second Inverter is made by connecting pin 2 to VDD, pin 4 to VSS, pins 1 and 5 are connected together as the output and with pin 3 as the input.

The third inverter is made by connecting pin 11 to VDD, pin 9 to VSS, pin 12 is the output and pin 10 is the input.

These three inverters can be used to construct the three inverters in figure 3 for example.

university/courses/electronics/electronics-lab-voltage-level-shifter.txt · Last modified: 24 Jul 2017 16:14 by amiclaus