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university:courses:electronics:electronics-lab-scr [07 Feb 2022 15:16] Doug Mercer [Activity: Silicon Controlled Rectifiers (SCR)] |
university:courses:electronics:electronics-lab-scr [27 May 2022 21:00] Doug Mercer [LATCH-UP] |
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| Latch-up is a potentially destructive situation in which a parasitic SCR is triggered, shorting the | Latch-up is a potentially destructive situation in which a parasitic SCR is triggered, shorting the | ||
| - | positive and negative supplies together. If current flow is not limited, electrical overstress will | + | positive and negative supplies together. If current flow is not limited, electrical over-stress will |
| occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and | occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and | ||
| wells form a four layer PNPN SCR structure when one of the two parasitic base-emitter junctions is | wells form a four layer PNPN SCR structure when one of the two parasitic base-emitter junctions is | ||
| - | momentarily forward biased during an overvoltage upset event. The SCR turns on and essentially causes a | + | momentarily forward biased during an over-voltage upset event. The SCR turns on and essentially causes a |
| short between the V<sub>DD</sub> power supply and ground. | short between the V<sub>DD</sub> power supply and ground. | ||
| Line 175: | Line 175: | ||
| <WRAP centeralign> Figure 6 Cross-section of PMOS and NMOS devices, with parasitic transistors Q<sub>1</sub> and Q<sub>2</sub> </WRAP> | <WRAP centeralign> Figure 6 Cross-section of PMOS and NMOS devices, with parasitic transistors Q<sub>1</sub> and Q<sub>2</sub> </WRAP> | ||
| - | Proper design methods to reduce the possiblility of SCR formation include increasing the spacing between | + | Proper design methods to reduce the possibility of SCR formation include increasing the spacing between |
| - | NMOS and PMOS devices and interposing highly doped regions bweteen and around Nwells and Pwells. Both of | + | NMOS and PMOS devices and interposing highly doped regions between and around Nwells and Pwells. Both of |
| these kinds of layout approaches attempt to lower the ß of either the vertical PNP or the lateral NPN | these kinds of layout approaches attempt to lower the ß of either the vertical PNP or the lateral NPN | ||
| parasitic bipolar transistors to less than 1. Some of these methods also tend to lower the resistance of | parasitic bipolar transistors to less than 1. Some of these methods also tend to lower the resistance of | ||
| Line 188: | Line 188: | ||
| </WRAP> | </WRAP> | ||
| - | **For Further Reading:** | + | =====The Programmable UJT (PUT)===== |
| - | http://en.wikipedia.org/wiki/Silicon-controlled_rectifier | + | The Programmable unijunction transistor or PUT is a close relative of other four layer devices in the thyristor family. Its has a four layered construction just like the SCR and has three terminals named anode(A), cathode(K) and gate(G) again like the thyristors. Background and example circuits that use the PUT can be found in this [[:university:courses:alm1k:alm-lab-scr#programmable_ujt_put|ADALM1000 Lab Activity]]. |
| - | [[adi>static/imported-files/application_notes/AN-397.pdf| Electrically Induced Damage to Standard Linear Integrated Circuits]] | + | **For Further Reading:** |
| + | [[http://en.wikipedia.org/wiki/Silicon-controlled_rectifier|The Silicon Controlled Rectifier]]\\ | ||
| + | [[adi>static/imported-files/application_notes/AN-397.pdf| Electrically Induced Damage to Standard Linear Integrated Circuits]]\\ | ||
| [[adi>library/analogDialogue/archives/35-05/latchup/latchup.pdf|Winning the Battle Against Latch-up in CMOS Analog Switches]] | [[adi>library/analogDialogue/archives/35-05/latchup/latchup.pdf|Winning the Battle Against Latch-up in CMOS Analog Switches]] | ||
university/courses/electronics/electronics-lab-scr.txt · Last modified: 27 May 2022 21:00 by Doug Mercer