This version is outdated by a newer approved version.
This version (27 Mar 2019 12:10) was approved by Antoniu Miclaus.The Previously approved version (05 Mar 2019 11:07) is available.
This version (27 Mar 2019 12:10) was approved by Antoniu Miclaus.The Previously approved version (05 Mar 2019 11:07) is available.This is an old revision of the document!
Table of Contents
Activity 5M. MOS transistor common source amplifier
Ojective:
The purpose of this activity is to investigate the common source configuration of the MOS transistor.
Materials:
ADALM2000 Active Learning Module
Solder-less breadboard
5 - Resistors
1 - 50 KΩ Variable resistor, potentiometer
1 - small signal NMOS transistor (enhancement mode ZVN2110A or CD4007)
Directions:
The configuration, shown in figure 1, demonstrates the NMOS transistor used as the common source amplifier. Output load resistor RL is chosen such that, for the desired nominal drain current ID, the voltage appearing at VDS is approximately half way between Vp and Vn (0 volts). Adjustable resistor Rpot a sets the nominal bias operating point for the transistor (VGS) to set the required ID. Voltage divider R1/R2 is chosen to provide a sufficiently large attenuation of the input stimulus from waveform generator W1 such that the amplitude of W1 is approximately the same as the signal amplitude seen at VDS.. This is done to more easily view the waveform generator W1 signal, given the rather small signal that will appear at the gate of the transistor, VGS. The attenuated W1 signal is AC coupled into the gate of the transistor with 4.7 uF C1so as not to disturb the DC bias condition.
Figure 1 Common source amplifier test configuration
Hardware Setup:
The waveform generator W1 should be configured for a 1 KHz Sine wave with 3 volt amplitude and 0 volt offset. The setup should be configured with scope channel 1+ connected to display the output W1. Scope channel 2 (2+) is used to measure alternately the waveform at the gate and drain of M1.
Figure 2 Common source amplifier test configuration breadboard connection
Procedure:
Figure 3 Common source amplifier test circuit, Scopy plot
The voltage gain, A, of the common source amplifier can be expressed as the ratio of load resistor RL to the small signal source resistance rs. The transconductance, gm, of the transistor is a function of the drain current ID and the so called gate overdrive voltage, VGS-Vth where Vth is the threshold voltage.
(1)
The small signal source resistance is 1/gm and can be viewed as being in series with the source. Now with a signal applied to the gate the same current flows in rs and the drain load RL. Thus the gain A is given by RL times gm.
(2)
Adding source degeneration
Objective:
The purpose of this activity is to investigate effect of the addition of source degeneration.
Additional Materials:
1 - 5KΩ Variable resistor, potentiometer
Directions:
Disconnect the source of M1 from ground and insert RS, a 5KΩ potentiometer, as shown in the following diagram. Adjust RS while noting the output signal seen at the drain of the transistor.
Figure 4 Source degeneration added
Hardware Setup
Figure 5 Source degeneration added, breadboard connection
Procedure:
Figure 6 Source degeneration added, Scopy plot
Questions:
What effect does adding RS have to the DC operating point of the circuit and how much would you need to adjust Rpot to return the circuit to the same DC bias (ID) you had in figure 1?
What is the effect on the voltage gain, A, by increasing RS? Write down the new gain equation similar to equation (2) above.
Source degeneration gain equation:
Increasing AC gain of source degenerated amplifier
Adding the source degeneration resistor has improved the stability of the DC operating point at the cost decreased amplifier gain. A higher gain for AC signals can be restored to some extent by adding capacitor C2across the degeneration resistor RS as shown in figure 4.
Figure 7 C2 added to increase AC gain
Hardware Setup
Figure 8 C2 added, breadboard connection
Procedure:
Figure 9 C2 added, Scopy plot
Self-biased configuration with negative feedback
Figure 10 Self Biased configuration
Hardware Setup
Figure 11 Self Biased configuration, breadboard connection
Procedure:
Figure 12 Self Biased configuration, Scopy plot
Questions:
How does adding negative feedback help to stabilize the DC operating point?
Resources:
- Fritzing files: comm_source_amp_bb
- LTspice files: comm_source_amp_ltspice
References for further reading:
http://en.wikipedia.org/wiki/Common_source_amplifier
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university/courses/electronics/electronics-lab-5m.1553685030.txt.gz · Last modified: 27 Mar 2019 12:10 by Antoniu Miclaus