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university:courses:electronics:electronics-lab-31 [14 Dec 2018 11:33]
amiclaus add Fritzing files
university:courses:electronics:electronics-lab-31 [05 Mar 2019 12:39] (current)
amiclaus [Bonus Step 3 Directions:]
Line 98: Line 98:
 Depending on the divide factor N of the particular divider you build you will need to change the F<​sub>​REF</​sub>​ input frequency by that amount. For example with N = 8, if F<​sub>​REF</​sub>​ was 250 KHz before the new F<​sub>​REF</​sub>​ would be 250/8 or 31.25 KHz. The frequency of the pulses at the output of the XOR gate phase detector will also be 8 times lower. Depending on the divide factor N of the particular divider you build you will need to change the F<​sub>​REF</​sub>​ input frequency by that amount. For example with N = 8, if F<​sub>​REF</​sub>​ was 250 KHz before the new F<​sub>​REF</​sub>​ would be 250/8 or 31.25 KHz. The frequency of the pulses at the output of the XOR gate phase detector will also be 8 times lower.
  
 +<WRAP round download>​
 **Resources:​** **Resources:​**
   * Fritzing files: [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​fritzing/​phase_locked_loop_bb | phase_locked_loop_bb]]   * Fritzing files: [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​fritzing/​phase_locked_loop_bb | phase_locked_loop_bb]]
 +</​WRAP>​
  
 **For Further Reading:** **For Further Reading:**
university/courses/electronics/electronics-lab-31.txt · Last modified: 05 Mar 2019 12:39 by amiclaus