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university:courses:electronics:electronics-lab-29 [14 Jun 2022 14:13] Doug Mercer [Background:] |
university:courses:electronics:electronics-lab-29 [06 Sep 2022 08:58] Antoniu Miclaus |
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| =====Background:===== | =====Background:===== | ||
| - | To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the ADALP2000 Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the | + | To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the ADALP2000 Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the to the Drain terminal of the PMOS on pin 12. |
| {{ :university:courses:alm1k:cd4007_pinout.png?400 |}} | {{ :university:courses:alm1k:cd4007_pinout.png?400 |}} | ||
university/courses/electronics/electronics-lab-29.txt · Last modified: 06 Sep 2022 08:58 by Antoniu Miclaus