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university:courses:electronics:electronics-lab-29 [23 Mar 2017 16:56]
Doug Mercer [Materials:]
university:courses:electronics:electronics-lab-29 [06 Sep 2022 08:58]
Antoniu Miclaus
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 =====Background:​===== =====Background:​=====
  
-To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the Drain terminal of the PMOS on pin 12.+To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the ADALP2000 ​Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the to the Drain terminal of the PMOS on pin 12.  
  
-{{ :​university:​courses:​electronics:cd4007.png?400 |}}+{{ :​university:​courses:​alm1k:cd4007_pinout.png?400 |}}
  
 <WRAP centeralign>​ Figure 1: CD4007 functional diagram. </​WRAP>​ <WRAP centeralign>​ Figure 1: CD4007 functional diagram. </​WRAP>​
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 We will now combine the double transmission gate built with inverter chain of the previous exercise to build a D-latch as shown in Figure 2. The two transmission gates work in tandem to realize the D-latch. During the transparent phase of the latch, when CLK=0, the first transmission gate (left) is ON while the second (right) is OFF. D is transmitted to the output (Q) through the first transmission gate and the two series connected inverters. During the latched phase of the latch, when CLK=1, the first transmission gate is OFF but the second transmission gate is ON. As a result, any change in the input D is not reflected at the output Q. However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed positive feedback loop formed around the two inverters in series. We will now combine the double transmission gate built with inverter chain of the previous exercise to build a D-latch as shown in Figure 2. The two transmission gates work in tandem to realize the D-latch. During the transparent phase of the latch, when CLK=0, the first transmission gate (left) is ON while the second (right) is OFF. D is transmitted to the output (Q) through the first transmission gate and the two series connected inverters. During the latched phase of the latch, when CLK=1, the first transmission gate is OFF but the second transmission gate is ON. As a result, any change in the input D is not reflected at the output Q. However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed positive feedback loop formed around the two inverters in series.
-Build the D-latch circuit shown in figure 2 on your solder-less breadboard. Use the CD4007 CMOS array for devices M<​sub>​1-6</​sub>​ and one ZVN2110A NMOS and ZVP2110A PMOS for each the two inverter stages M<​sub>​7,​8</​sub>​ and M<​sub>​9,​10</​sub>​. Use the fixed +5 V power supply from Analog Discovery ​to power your circuit.+Build the D-latch circuit shown in figure 2 on your solder-less breadboard. Use the CD4007 CMOS array for devices M<​sub>​1-6</​sub>​ and one ZVN2110A NMOS and ZVP2110A PMOS for each the two inverter stages M<​sub>​7,​8</​sub>​ and M<​sub>​9,​10</​sub>​. Use the fixed +5 V power supply from ADALM2000 ​to power your circuit.
  
 {{ :​university:​courses:​electronics:​adff_f2.png?​600 |}} {{ :​university:​courses:​electronics:​adff_f2.png?​600 |}}
  
-<WRAP centeralign>​ Figure 2D Type Latch </​WRAP>​+<WRAP centeralign>​ Figure 2 D Type Latch </​WRAP>​
  
 =====Hardware Setup:===== =====Hardware Setup:=====
  
 Configure both AWG outputs as DC sources for the first steps of the lab. The scope channels are to be used to monitor the inputs and outputs of the circuit as needed. The fixed +5 V power supply is to be used to power your circuit. The fixed -5V supply should be disabled during this Lab. Configure both AWG outputs as DC sources for the first steps of the lab. The scope channels are to be used to monitor the inputs and outputs of the circuit as needed. The fixed +5 V power supply is to be used to power your circuit. The fixed -5V supply should be disabled during this Lab.
 +{{ :​university:​courses:​electronics:​adff_f2bb.png?​ |}}
 +
 +<WRAP centeralign>​ Figure 3 D Type Latch Breadboard connections </​WRAP>​
 +
  
 =====Procedure:​===== =====Procedure:​=====
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 Observe the output Q of the latch on scope Channel 2. A steady +5 V should appear on the scope screen. Capture a screen shot. Observe the output Q of the latch on scope Channel 2. A steady +5 V should appear on the scope screen. Capture a screen shot.
 +{{ :​university:​courses:​electronics:​adff_ss1.png?​600 |}}
 +
 +<WRAP centeralign>​ Figure 4 Scopy screenshot </​WRAP>​
  
 Apply logic Low to the D input by setting AWG1 to 0 V DC. Observe the output on the scope. This is the transparent phase of the latch. You should see that scope channel 2 is also at 0 V DC. Apply logic Low to the D input by setting AWG1 to 0 V DC. Observe the output on the scope. This is the transparent phase of the latch. You should see that scope channel 2 is also at 0 V DC.
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 Observe the Q output on the scope screen. A steady low should appear in spite of changing D to logic High since the previous value at D-input was low. Capture a screen shot. This is the latched phase of the circuit. Observe the Q output on the scope screen. A steady low should appear in spite of changing D to logic High since the previous value at D-input was low. Capture a screen shot. This is the latched phase of the circuit.
 +{{ :​university:​courses:​electronics:​adff_ss2.png?​600 |}}
  
-Now configure both AWG channels as square waves with 2.5 V amplitudes ​and 2.5 V offsets ( 0 to 5 V swings). Set AWG1 to a frequency of 1 KHz and AWG2 to a frequency of 2 KHz or twice AWG1. Set the phase of AWG2 to 270 degrees. Be sure to set the AWGs to run synchronously.+<WRAP centeralign>​ Figure 5 Scopy screenshot </​WRAP>​ 
 + 
 +Now configure both AWG channels as square waves with 5 V amplitudes ​peak-to-peak. Set AWG1 to a frequency of 1 KHz and AWG2 to a frequency of 2 KHz or twice AWG1. Set the phase of AWG2 to degrees. Be sure to set the AWGs to run synchronously.
  
 Observe the Q output on the scope screen with respect to the signals seen at the CLK and D inputs. Capture the various waveforms and save a screen shot for inclusion in your lab report. Observe the Q output on the scope screen with respect to the signals seen at the CLK and D inputs. Capture the various waveforms and save a screen shot for inclusion in your lab report.
 +{{ :​university:​courses:​electronics:​adff_ss3.png?​600 |}}
  
-Now set the phase of AWG2 to 90 degrees. Again observe the Q output on the scope screen with respect to the signals seen at the CLK and D inputs. How have they changed compared to when the phase of AWG2 was 270 degrees and explain why? Capture the various waveforms and save a screen shot for inclusion in your lab report.+<WRAP centeralign>​ Figure 6 Scopy screenshot </​WRAP>​ 
 + 
 +Now set the phase of AWG2 to 90 degrees. Again observe the Q output on the scope screen with respect to the signals seen at the CLK and D inputs. How have they changed compared to when the phase of AWG2 was degrees and explain why? Capture the various waveforms and save a screen shot for inclusion in your lab report. 
 +{{ :​university:​courses:​electronics:​adff_ss4.png?​600 |}} 
 + 
 +<WRAP centeralign>​ Figure 8 Scopy screenshot </​WRAP>​
  
 =====Questions:​===== =====Questions:​=====
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 The D-Type latch shown in figure 2 uses complementary pass gates with both NMOS and PMOS transistors. Individual NMOS or PMOS cannot pass both high and low logic levels with equal strength (i.e. on resistance). A single NMOS device can pass a strong logic 0 but will pass a weak logic 1. Conversely, a single PMOS device can pass a strong logic 1 but will pass a weak logic 0. The D-Type latch shown in figure 2 uses complementary pass gates with both NMOS and PMOS transistors. Individual NMOS or PMOS cannot pass both high and low logic levels with equal strength (i.e. on resistance). A single NMOS device can pass a strong logic 0 but will pass a weak logic 1. Conversely, a single PMOS device can pass a strong logic 1 but will pass a weak logic 0.
  
-For many design cases in integrated circuits where internal signals just pass between internal circuit blocks, the asymmetric drive of a single NMOS or PMOS transistor pass is not a significant issue. The positive feedback inherent in a latch can help in this case. In those cases a simplified D-Type latch that uses just 6 devices rather than the 10 used in figure 2 is shown in figures ​( latches on rising edge ) and ( latches on falling edge ).+For many design cases in integrated circuits where internal signals just pass between internal circuit blocks, the asymmetric drive of a single NMOS or PMOS transistor pass is not a significant issue. The positive feedback inherent in a latch can help in this case. In those cases a simplified D-Type latch that uses just 6 devices rather than the 10 used in figure 2 is shown in figures ​( latches on rising edge ) and 10 ( latches on falling edge ).
  
 {{ :​university:​courses:​electronics:​adff_f3.png?​500 |}} {{ :​university:​courses:​electronics:​adff_f3.png?​500 |}}
  
-<WRAP centeralign>​ Figure ​6 transistor rising edge D-Type latch </​WRAP>​+<WRAP centeralign>​ Figure ​6 transistor rising edge D-Type latch </​WRAP>​
  
 {{ :​university:​courses:​electronics:​adff_f4.png?​500 |}} {{ :​university:​courses:​electronics:​adff_f4.png?​500 |}}
  
-<WRAP centeralign>​ Figure ​6 transistor falling edge D-Type latch </​WRAP>​+<WRAP centeralign>​ Figure ​10 6 transistor falling edge D-Type latch </​WRAP>​ 
 +=====Hardware Setup:​===== 
 +{{ :​university:​courses:​electronics:​adff_f9bb.png?​ |}} 
 + 
 +<WRAP centeralign>​ Figure 11 6 transistor rising edge D-Type latch Breadboard connections </​WRAP>​ 
 + 
 +{{ :​university:​courses:​electronics:​adff_f10bb.png?​ |}} 
 + 
 +<WRAP centeralign>​ Figure 12 6 transistor falling edge D Type Latch Breadboard connections ​</​WRAP>​
  
 =====Directions:​===== =====Directions:​=====
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 The pair of inverters made using the four individual NMOS and PMOS transistors (ZVN2110A and ZVP2110A) could also be constructed from a second CD4007 IC or could be CMOS inverters from a Hex Inverter IC such as a 74HC04 or CD4049. The pair of inverters made using the four individual NMOS and PMOS transistors (ZVN2110A and ZVP2110A) could also be constructed from a second CD4007 IC or could be CMOS inverters from a Hex Inverter IC such as a 74HC04 or CD4049.
 +
 +<WRAP round download>​
 +**Resources:​**
 +  * Fritzing files: [[downgit>​education_tools/​tree/​master/​m2k/​fritzing/​cmos_dtype_latch_bb | cmos_dtype_latch_bb]]
 +  * LTSpice files: [[downgit>​education_tools/​tree/​master/​m2k/​ltspice/​cmos_dtype_latch_ltspice | cmos_dtype_latch_ltspice]]
 +</​WRAP>​
  
 **For Further Reading:** **For Further Reading:**
  
-Electronic Latches [[http://​en.wikipedia.org/​wiki/​Flip-flop_(electronics)]]+Electronic Latches [[wp>Flip-flop_(electronics)]]
  
 **Return to Lab Activity [[university:​courses:​electronics:​labs|Table of Contents]].** **Return to Lab Activity [[university:​courses:​electronics:​labs|Table of Contents]].**
university/courses/electronics/electronics-lab-29.txt · Last modified: 06 Sep 2022 08:58 by Antoniu Miclaus