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university:courses:electronics:electronics-lab-29 [23 Mar 2017 16:56]
Doug Mercer [Materials:]
university:courses:electronics:electronics-lab-29 [24 Apr 2017 08:48]
Antoniu Miclaus rename
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 =====Background:​===== =====Background:​=====
  
-To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the Drain terminal of the PMOS on pin 12.+To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the ADALP2000 ​Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the Drain terminal of the PMOS on pin 12.
  
 {{ :​university:​courses:​electronics:​cd4007.png?​400 |}} {{ :​university:​courses:​electronics:​cd4007.png?​400 |}}
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 We will now combine the double transmission gate built with inverter chain of the previous exercise to build a D-latch as shown in Figure 2. The two transmission gates work in tandem to realize the D-latch. During the transparent phase of the latch, when CLK=0, the first transmission gate (left) is ON while the second (right) is OFF. D is transmitted to the output (Q) through the first transmission gate and the two series connected inverters. During the latched phase of the latch, when CLK=1, the first transmission gate is OFF but the second transmission gate is ON. As a result, any change in the input D is not reflected at the output Q. However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed positive feedback loop formed around the two inverters in series. We will now combine the double transmission gate built with inverter chain of the previous exercise to build a D-latch as shown in Figure 2. The two transmission gates work in tandem to realize the D-latch. During the transparent phase of the latch, when CLK=0, the first transmission gate (left) is ON while the second (right) is OFF. D is transmitted to the output (Q) through the first transmission gate and the two series connected inverters. During the latched phase of the latch, when CLK=1, the first transmission gate is OFF but the second transmission gate is ON. As a result, any change in the input D is not reflected at the output Q. However, the second transmission gate, which is now turned ON ensures that the previous logic level at Q is retained through the closed positive feedback loop formed around the two inverters in series.
-Build the D-latch circuit shown in figure 2 on your solder-less breadboard. Use the CD4007 CMOS array for devices M<​sub>​1-6</​sub>​ and one ZVN2110A NMOS and ZVP2110A PMOS for each the two inverter stages M<​sub>​7,​8</​sub>​ and M<​sub>​9,​10</​sub>​. Use the fixed +5 V power supply from Analog Discovery ​to power your circuit.+Build the D-latch circuit shown in figure 2 on your solder-less breadboard. Use the CD4007 CMOS array for devices M<​sub>​1-6</​sub>​ and one ZVN2110A NMOS and ZVP2110A PMOS for each the two inverter stages M<​sub>​7,​8</​sub>​ and M<​sub>​9,​10</​sub>​. Use the fixed +5 V power supply from ADALM2000 ​to power your circuit.
  
 {{ :​university:​courses:​electronics:​adff_f2.png?​600 |}} {{ :​university:​courses:​electronics:​adff_f2.png?​600 |}}
university/courses/electronics/electronics-lab-29.txt · Last modified: 06 Sep 2022 08:58 by Antoniu Miclaus