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university:courses:electronics:electronics-lab-28 [24 Jul 2017 16:13] – change amplitude value to peak-peak Antoniu Miclausuniversity:courses:electronics:electronics-lab-28 [14 Jun 2022 14:11] (current) – [Making inverters with the CD4007 transistor array] Doug Mercer
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-====== Build CMOS Logic Functions Using CD4007 Array ======+====== Build CMOS Logic Functions Using CD4007 Array - ADALM2000======
  
 ===== Objective: ===== ===== Objective: =====
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 Below in figure 1 is the schematic and pinout for the CD4007: Below in figure 1 is the schematic and pinout for the CD4007:
  
-{{ :university:courses:electronics:cd4007.png?350 |}}+{{ :university:courses:alm1k:cd4007_pinout.png?400 |}}
  
 <WRAP centeralign> Figure 1 CD4007 CMOS transistor array pinout </WRAP> <WRAP centeralign> Figure 1 CD4007 CMOS transistor array pinout </WRAP>
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 ===== Hardware Setup: ===== ===== Hardware Setup: =====
  
-Configure the waveform generator for a 1 KHz triangle wave with 5V amplitude and 2.5V offset. Both scope channels should be set to 1V/Div. Configure the scope in XY mode with channel 1 on the horizontal axis and channel 2 on the vertical axis.+Configure the waveform generator for a 100 Hz triangle wave with 5V amplitude peak-to-peak and 2.5V offset. Both scope channels should be set to 1V/Div. Configure the scope in XY mode with channel 1 on the horizontal axis and channel 2 on the vertical axis. 
 +{{ :university:courses:electronics:a28_f3bb.JPG? |}} 
 + 
 +<WRAP centeralign> Figure 4 Breadboard connections Setup to measure input threshold and transition region </WRAP> 
  
 ===== Procedure: ===== ===== Procedure: =====
  
-First using scope channel 2 to measure the inverter output voltage vs. the input as the input is swept from 0 to 5V obtain a plot like the top curve in figure 4. Export the data to a .csv file and extract the width of the transition region and the threshold voltage at the input at the point where the output voltage is exactly 1/2 V<sub>DD</sub>+First using scope channel 2 to measure the inverter output voltage vs. the input as the input is swept from 0 to 5V obtain a plot like the top curve in figure 5. Export the data to a .csv file and extract the width of the transition region and the threshold voltage at the input at the point where the output voltage is exactly 1/2 V<sub>DD</sub>
  
-Next move the channel 2 scope inputs 2+ and 2- to measure the voltage across the 100Ω resistor, R<sub>1</sub>, in figure 3. You may need to adjust the vertical scale of channel 2 for an optimal view of the current waveform. Now obtain a plot of I<sub>D</sub> vs. the input as the input is swept from 0 to 5V. This should give you a plot much like the bottom curve in figure 4. Export the data to a .csv file and extract the peak current ( measured voltage divided by the 100Ω resistor value) and the input and output voltages where the peak occurred.+Next move the channel 2 scope inputs 2+ and 2- to measure the voltage across the 100Ω resistor, R<sub>1</sub>, in figure 3. You may need to adjust the vertical scale of channel 2 for an optimal view of the current waveform. Now obtain a plot of I<sub>D</sub> vs. the input as the input is swept from 0 to 5V. This should give you a plot much like the bottom curve in figure 5. Export the data to a .csv file and extract the peak current ( measured voltage divided by the 100Ω resistor value) and the input and output voltages where the peak occurred.
  
 {{ :university:courses:electronics:a28_f4.png?450 |}} {{ :university:courses:electronics:a28_f4.png?450 |}}
  
-<WRAP centeralign> Figure Inverter output voltage and supply current curves vs. input voltage </WRAP>+<WRAP centeralign> Figure Inverter output voltage and supply current curves vs. input voltage </WRAP> 
 +{{ :university:courses:electronics:a28_f4a.png?500 |}} 
 + 
 +<WRAP centeralign> Figure 6 Scopy screenshots: Inverter output voltage and supply current curves vs. input voltage </WRAP> 
  
 The input to output transfer characteristic plots the output voltage V<sub>OUT</sub> versus the input voltage V<sub>IN</sub>. Notice that when the input voltage increase from 0V to 5V the output voltage decreases from 5V to 0V. The supply current characteristic plots the current flowing through the transistors between V<sub>DD</sub> and ground also versus the input voltage V<sub>IN</sub>. The fact that there are two parts of the characteristic curves when the input voltage is near ground and V<sub>DD</sub>, no current flows between V<sub>DD</sub> and ground, is very attractive because there is no power dissipation at this stages. This very fact is the reason that today nearly all digital circuitry is now build using CMOS technology. The input to output transfer characteristic plots the output voltage V<sub>OUT</sub> versus the input voltage V<sub>IN</sub>. Notice that when the input voltage increase from 0V to 5V the output voltage decreases from 5V to 0V. The supply current characteristic plots the current flowing through the transistors between V<sub>DD</sub> and ground also versus the input voltage V<sub>IN</sub>. The fact that there are two parts of the characteristic curves when the input voltage is near ground and V<sub>DD</sub>, no current flows between V<sub>DD</sub> and ground, is very attractive because there is no power dissipation at this stages. This very fact is the reason that today nearly all digital circuitry is now build using CMOS technology.
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 In this section we will investigate the dynamic properties of the CMOS inverter, that is, its behavior during the time when switching the input signal from low-to-high or high-to-low voltages and the associated power dissipation. In this section we will investigate the dynamic properties of the CMOS inverter, that is, its behavior during the time when switching the input signal from low-to-high or high-to-low voltages and the associated power dissipation.
  
-We now consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms are shown in figure 5. Delay characterization of the dynamic behavior of an inverter is given by two propagation delay times, T<sub>HL</sub> and T<sub>LH</sub> as illustrated in figure 5. Note that these propagation times are specified with respect to the mid supply voltage V<sub>DD</sub>/2.+We now consider a CMOS inverter driven by a voltage pulse. Typical input/output waveforms are shown in figure 5. Delay characterization of the dynamic behavior of an inverter is given by two propagation delay times, T<sub>HL</sub> and T<sub>LH</sub> as illustrated in figure 7. Note that these propagation times are specified with respect to the mid supply voltage V<sub>DD</sub>/2.
  
 {{ :university:courses:electronics:a28_f5.png?450 |}} {{ :university:courses:electronics:a28_f5.png?450 |}}
  
-<WRAP centeralign> Figure CMOS Inverter propagation delay </WRAP>+<WRAP centeralign> Figure CMOS Inverter propagation delay </WRAP>
  
 {{ :university:courses:electronics:a28_f6.png?600 |}} {{ :university:courses:electronics:a28_f6.png?600 |}}
  
-<WRAP centeralign> Figure CMOS Inverter rise / fall time </WRAP>+<WRAP centeralign> Figure CMOS Inverter rise / fall time </WRAP> 
  
 ===== Hardware Setup: ===== ===== Hardware Setup: =====
  
-Now configure the waveform generator for a 500 KHz square wave with 5V amplitude and 2.5V offset. Be sure to reconnect scope channel 2 to measure the output voltage waveform. Both scope channels should be set to 1V/Div. Adjust the horizontal scale so that you can view both the rising and falling edges of the input and output waveforms similar to what is shown in figures and 6.+Now configure the waveform generator for a 500 KHz square wave with 5V amplitude peak-to-peak and 2.5V offset. Be sure to reconnect scope channel 2 to measure the output voltage waveform. Both scope channels should be set to 1V/Div. Adjust the horizontal scale so that you can view both the rising and falling edges of the input and output waveforms similar to what is shown in figures and 8. 
 +{{ :university:courses:electronics:a28_nf9a.PNG? |}} 
 + 
 +<WRAP centeralign> Figure 9 CMOS inverter Breadboard connections </WRAP> 
 + 
 +{{ :university:courses:electronics:a28_f10a.JPG?500 |}} 
 + 
 +<WRAP centeralign> Figure 10 Scopy screenshot: CMOS Inverter propagation delay </WRAP> 
  
 ===== Measurements: ===== ===== Measurements: =====
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 ===== Making a CMOS Schmitt Trigger with the CD4007 transistor array ===== ===== Making a CMOS Schmitt Trigger with the CD4007 transistor array =====
  
-The input of the Schmitt trigger, as shown in figure 7, is tied to the gates of four stacked devices. The upper two are PMOS and the lower two are NMOS. Transistors M<sub>5</sub> and M<sub>6</sub> operate as source followers and introduce hysteresis by feeding back the output voltage, V<sub>OUT</sub>, to the two points in the stack midway between the two NMOS and two PMOS devices.+The input of the Schmitt trigger, as shown in figure 11, is tied to the gates of four stacked devices. The upper two are PMOS and the lower two are NMOS. Transistors M<sub>5</sub> and M<sub>6</sub> operate as source followers and introduce hysteresis by feeding back the output voltage, V<sub>OUT</sub>, to the two points in the stack midway between the two NMOS and two PMOS devices.
  
 {{ :university:courses:electronics:a28_f7.png?600 |}} {{ :university:courses:electronics:a28_f7.png?600 |}}
  
-<WRAP centeralign> Figure CMOS Schmitt trigger circuit </WRAP>+<WRAP centeralign> Figure 11 CMOS Schmitt trigger circuit </WRAP>
  
 When V<sub>IN</sub> is at 0V, transistors M<sub>1</sub> and M<sub>3</sub> are on, and M<sub>2</sub>, M<sub>4</sub> and M<sub>5</sub> are off. Since V<sub>OUT</sub> is high, M<sub>6</sub> is on and acts as a source follower, the drain of M<sub>2</sub>, which is also the source of M<sub>4</sub>, is at V<sub>DD</sub> - V<sub>TH</sub>. If the input voltage is ramped up to one threshold above ground transistor M<sub>2</sub> begins to turn on, M<sub>2</sub> and M<sub>6</sub> both being on form a voltage divider network biasing the source of M4 at roughly half the supply. When the input is a threshold above 1/2 V<sub>DD</sub>, M<sub>4</sub> begins to turn on and regenerative switching is about to take over. Any more voltage on the input causes V<sub>OUT</sub> to drop. When V<sub>OUT</sub> drops, the source of M<sub>6</sub> follows its gate, which is V<sub>OUT</sub>, the influence of M<sub>6</sub> in the voltage divider with M<sub>2</sub> rapidly diminishes, bringing V<sub>OUT</sub> down further yet. Meanwhile M<sub>5</sub> has started to turn on, its gate being brought low by the rapidly dropping V<sub>OUT</sub>. M<sub>5</sub> turning on brings the source of M<sub>3</sub> low and turns M<sub>3</sub> off. With M<sub>3</sub> off, V<sub>OUT</sub> will collapse all the way down to ground. The snapping action is due to greater than unity loop gain through the stack caused by positive feedback through the source follower transistors. When the input is brought low again a similar process occurs in the upper portion of the stack and the snapping action takes place when the lower threshold its reached. When V<sub>IN</sub> is at 0V, transistors M<sub>1</sub> and M<sub>3</sub> are on, and M<sub>2</sub>, M<sub>4</sub> and M<sub>5</sub> are off. Since V<sub>OUT</sub> is high, M<sub>6</sub> is on and acts as a source follower, the drain of M<sub>2</sub>, which is also the source of M<sub>4</sub>, is at V<sub>DD</sub> - V<sub>TH</sub>. If the input voltage is ramped up to one threshold above ground transistor M<sub>2</sub> begins to turn on, M<sub>2</sub> and M<sub>6</sub> both being on form a voltage divider network biasing the source of M4 at roughly half the supply. When the input is a threshold above 1/2 V<sub>DD</sub>, M<sub>4</sub> begins to turn on and regenerative switching is about to take over. Any more voltage on the input causes V<sub>OUT</sub> to drop. When V<sub>OUT</sub> drops, the source of M<sub>6</sub> follows its gate, which is V<sub>OUT</sub>, the influence of M<sub>6</sub> in the voltage divider with M<sub>2</sub> rapidly diminishes, bringing V<sub>OUT</sub> down further yet. Meanwhile M<sub>5</sub> has started to turn on, its gate being brought low by the rapidly dropping V<sub>OUT</sub>. M<sub>5</sub> turning on brings the source of M<sub>3</sub> low and turns M<sub>3</sub> off. With M<sub>3</sub> off, V<sub>OUT</sub> will collapse all the way down to ground. The snapping action is due to greater than unity loop gain through the stack caused by positive feedback through the source follower transistors. When the input is brought low again a similar process occurs in the upper portion of the stack and the snapping action takes place when the lower threshold its reached.
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 ===== Directions: ===== ===== Directions: =====
  
-On your solder-less breadboard build the Schmitt trigger circuit shown in figure to test the input to output switching characteristics as you did with the plain inverter.+On your solder-less breadboard build the Schmitt trigger circuit shown in figure 11 to test the input to output switching characteristics as you did with the plain inverter.
  
 ===== Hardware Setup: ===== ===== Hardware Setup: =====
  
-Configure the waveform generator for a 1 KHz triangle wave with 5V amplitude and 2.5V offset. Both scope channels should be set to 1V/Div. Configure the scope in XY mode with channel 1 on the horizontal axis and channel 2 on the vertical axis.+Configure the waveform generator for a 1 KHz triangle wave with 5V amplitude peak-to-peak and 2.5V offset. Both scope channels should be set to 1V/Div. Configure the scope in XY mode with channel 1 on the horizontal axis and channel 2 on the vertical axis. 
 +{{ :university:courses:electronics:a28_f12a.png? |}} 
 + 
 +<WRAP centeralign> Figure 12 CMOS Schmitt trigger circuit breadboard connections</WRAP> 
  
 ===== Procedure: ===== ===== Procedure: =====
  
 Use scope channel 2 to measure the output voltage vs. the input as the input is swept from 0 to 5V obtain a plot like you did for the simple inverter. Export the data to a .csv file and extract the upper and lower threshold voltages and the width of the hysteresis region. Is the hysteresis region centered around 1/2 V<sub>DD</sub>? Use scope channel 2 to measure the output voltage vs. the input as the input is swept from 0 to 5V obtain a plot like you did for the simple inverter. Export the data to a .csv file and extract the upper and lower threshold voltages and the width of the hysteresis region. Is the hysteresis region centered around 1/2 V<sub>DD</sub>?
 +{{ :university:courses:electronics:a28_f13a.JPG?350 |}}
 +
 +<WRAP centeralign> Figure 13 CMOS Schmitt trigger Scopy plot </WRAP>
 +
  
 ===== Making a NAND / AND gate with the CD4007 transistor array ===== ===== Making a NAND / AND gate with the CD4007 transistor array =====
  
-As shown in figure 8, one 2 input NAND gate and one inverter can be built from one CD4007 package. Configure the NAND gate as shown below by connecting pins 12 and 13 together as the NAND output. Pin 14 and pin 11 is connected to V<sub>DD</sub> for power and pin 7 V<sub>SS</sub> to ground. Pin 9 should be tied to pin 8 to complete N side of the NAND gate. Pin 6 will be the A input and pin 10 will be the B input.+As shown in figure 14, one 2 input NAND gate and one inverter can be built from one CD4007 package. Configure the NAND gate as shown below by connecting pins 12 and 13 together as the NAND output. Pin 14 and pin 11 is connected to V<sub>DD</sub> for power and pin 7 V<sub>SS</sub> to ground. Pin 9 should be tied to pin 8 to complete N side of the NAND gate. Pin 6 will be the A input and pin 10 will be the B input.
  
 {{ :university:courses:electronics:a28_f8.png?600 |}} {{ :university:courses:electronics:a28_f8.png?600 |}}
  
-<WRAP centeralign> Figure 2 input NAND and Inverter </WRAP>+<WRAP centeralign> Figure 14 2 input NAND and Inverter </WRAP> 
 +{{ :university:courses:electronics:a28_f141.JPG? |}} 
 + 
 +<WRAP centeralign> Figure 14.1 2 input NAND breadboard connections </WRAP> 
 +{{ :university:courses:electronics:a28_f142.JPG? |}} 
 + 
 +<WRAP centeralign> Figure 14.2 2 input AND breadboard connections </WRAP> 
  
 The Inverter is made by connecting pin 2 to V<sub>DD</sub>, pin 4 to V<sub>SS</sub>, pins 1 and 5 are connected together as the output and with pin 3 as the input. An AND gate is made by connecting the output of the NAND at pins 12 and 13 to the inverter input at pin 3. The Inverter is made by connecting pin 2 to V<sub>DD</sub>, pin 4 to V<sub>SS</sub>, pins 1 and 5 are connected together as the output and with pin 3 as the input. An AND gate is made by connecting the output of the NAND at pins 12 and 13 to the inverter input at pin 3.
  
-A single 3 input NAND gate can be made by using all 6 devices as shown in figure 9.+A single 3 input NAND gate can be made by using all 6 devices as shown in figure 15.
  
 ===== Directions: ===== ===== Directions: =====
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 {{ :university:courses:electronics:a28_f9.png?600 |}} {{ :university:courses:electronics:a28_f9.png?600 |}}
  
-<WRAP centeralign> Figure 3 input NAND gate </WRAP>+<WRAP centeralign> Figure 15 3 input NAND gate </WRAP> 
 +{{ :university:courses:electronics:a28_f151.JPG? |}} 
 + 
 +<WRAP centeralign> Figure 15.1 3 input NAND breadboard connections </WRAP> 
  
 ===== Making a NOR / OR gate with the CD4007 transistor array ===== ===== Making a NOR / OR gate with the CD4007 transistor array =====
  
-As shown in figure 10, one 2 input NOR gate and one inverter can be built from one CD4007 package. Configure the NAND gate as shown below by connecting pins+As shown in figure 16, one 2 input NOR gate and one inverter can be built from one CD4007 package. Configure the NAND gate as shown below by connecting pins
  
 {{ :university:courses:electronics:a28_f10.png?600 |}} {{ :university:courses:electronics:a28_f10.png?600 |}}
  
-<WRAP centeralign> Figure 10 2 input NOR and Inverter </WRAP>+<WRAP centeralign> Figure 16 2 input NOR and Inverter </WRAP> 
 +{{ :university:courses:electronics:a28_f161.JPG? |}}
  
-A single 3 input NOR gate can be made by using all 6 devices as shown in figure 11.+<WRAP centeralign> Figure 16.1 2 input NOR breadboard connections </WRAP> 
 +{{ :university:courses:electronics:a28_f162.JPG? |}} 
 + 
 +<WRAP centeralign> Figure 16.2 2 input OR breadboard connections </WRAP> 
 + 
 + 
 +A single 3 input NOR gate can be made by using all 6 devices as shown in figure 17.
  
 ===== Directions: ===== ===== Directions: =====
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 {{ :university:courses:electronics:a28_f11.png?600 |}} {{ :university:courses:electronics:a28_f11.png?600 |}}
  
-<WRAP centeralign> Figure 11 3 input NOR gate </WRAP>+<WRAP centeralign> Figure 17 3 input NOR gate </WRAP> 
 +{{ :university:courses:electronics:a28_f171.JPG? |}} 
 + 
 +<WRAP centeralign> Figure 17.1 3 input NOR gate breadboard connections </WRAP> 
  
 By combining the two input NOR gate and the inverter along with an RC delay element a monostable By combining the two input NOR gate and the inverter along with an RC delay element a monostable
-multivibrator or one-shot can be constructed as shown in figure 12.+multivibrator or one-shot can be constructed as shown in figure 18.
  
 {{ :university:courses:electronics:a28_f13.png?600 |}} {{ :university:courses:electronics:a28_f13.png?600 |}}
  
-<WRAP centeralign> Figure 12 NOR gate One-Shot </WRAP>+<WRAP centeralign> Figure 18 NOR gate One-Shot </WRAP>
  
 The width of the output pulse is determined by R<sub>T</sub> and C<sub>T</sub> according to the following formula: The width of the output pulse is determined by R<sub>T</sub> and C<sub>T</sub> according to the following formula:
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 What happens if the trigger input is held high longer than τ?\\ What happens if the trigger input is held high longer than τ?\\
 What happens if more than one trigger pulse is applied during τ?\\ What happens if more than one trigger pulse is applied during τ?\\
-How would you modify the one-shot circuit in figure 12 to use a 2 input NAND gate in place of the NOR+How would you modify the one-shot circuit in figure 18 to use a 2 input NAND gate in place of the NOR
 gate? gate?
  
 ===== Making a SPDT Analog Switch with the CD4007 transistor array ===== ===== Making a SPDT Analog Switch with the CD4007 transistor array =====
  
-In addition to an analog SPDT switch this configuration is often called a pass gate or 2 into 1 MUX (multiplexer). The configuration is shown in figure 13.+In addition to an analog SPDT switch this configuration is often called a pass gate or 2 into 1 MUX (multiplexer). The configuration is shown in figure 19.
  
 {{ :university:courses:electronics:a28_f12.png?600 |}} {{ :university:courses:electronics:a28_f12.png?600 |}}
  
-<WRAP centeralign> Figure 13 Single Pole Double Throw CMOS Switch </WRAP>+<WRAP centeralign> Figure 19 Single Pole Double Throw CMOS Switch </WRAP>
  
 The on resistance, R<sub>ON</sub> of a pass gate or switch is an important specification. Please refer to the Activity on [[university:courses:electronics:electronics-lab-18|CMOS analog switches]] to find the procedure to measure the resistance of the NMOS, PMOS and combined CMOS switches. The on resistance, R<sub>ON</sub> of a pass gate or switch is an important specification. Please refer to the Activity on [[university:courses:electronics:electronics-lab-18|CMOS analog switches]] to find the procedure to measure the resistance of the NMOS, PMOS and combined CMOS switches.
  
 +<WRAP round download>
 +**Resources:**
 +  * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/cmos_logic_func_bb | cmos_logic_func_bb]]
 +  * LTspice files: [[downgit>education_tools/tree/master/m2k/ltspice/cmos_logic_func_ltspice | cmos_logic_func_ltspice]]
 +</WRAP>
 ===== For Further reading: ===== ===== For Further reading: =====
  
-4000 Series Logic and Analog Circuitry: http://www.analog.com/static/imported-files/rarely_asked_questions/4000_Series_Article.pdf\\+{{ :university:courses:4000_series_article.pdf|4000 Series Logic and Analog Circuitry}}\\
 CMOS Logic: http://en.wikipedia.org/wiki/CMOS\\ CMOS Logic: http://en.wikipedia.org/wiki/CMOS\\
 Noise Margin: http://en.wikipedia.org/wiki/Noise_margin\\ Noise Margin: http://en.wikipedia.org/wiki/Noise_margin\\
university/courses/electronics/electronics-lab-28.1500905613.txt.gz · Last modified: 24 Jul 2017 16:13 by Antoniu Miclaus