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| university:courses:electronics:electronics-lab-27 [05 Mar 2019 12:36] – [Questions:] Antoniu Miclaus | university:courses:electronics:electronics-lab-27 [08 Jul 2022 15:36] (current) – [Background:] Doug Mercer |
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| ====== Activity: TTL inverter and NAND gate ====== | ======Activity: TTL inverter and NAND gate, For ADALM2000====== |
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| ===== Objectives: ===== | ===== Objectives: ===== |
| <WRAP centeralign> Figure 1 TTL Inverter </WRAP> | <WRAP centeralign> Figure 1 TTL Inverter </WRAP> |
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| The input stage transistor Q<sub>1</sub> performs a current steering function. It can be thought of as a back-to-back diode arrangement. The transistor is operated in either forward or reverse mode to steer current to or from the second stage transistor's base, Q<sub>2</sub>. The forward current gain or ß<sub>F</sub>, is much larger than the reverse ß<sub>R</sub>. it provides a higher discharge current to discharge the base of when turning it off. | The input stage transistor Q<sub>1</sub> performs a current steering function. It can be thought of as a back-to-back diode arrangement. The transistor is operated in either forward or reverse mode to steer current to or from the second stage transistor's base, Q<sub>2</sub>. The forward current gain or ß<sub>F</sub>, is much larger than the reverse ß<sub>R</sub>. it provides a higher discharge current to discharge the base when turning it off. |
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| {{ :university:courses:electronics:a27_f2.png?500 |}} | {{ :university:courses:electronics:a27_f2.png?500 |}} |
| <WRAP centeralign> Figure 2 Equivalent circuit of input current steering stage </WRAP> | <WRAP centeralign> Figure 2 Equivalent circuit of input current steering stage </WRAP> |
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| Second stage transistor, Q<sub>2</sub> in figure 1, is a phase splitter driving transistor to drive both halves of the pull up and pull down output stage. It allows the input condition to be produced in opposite phases so that the output transistors can be driven in anti-phase. This allows Q<sub>3</sub> to be on when Q<sub>4</sub> is off and vice versa as shown in figure 3. | Second stage transistor, Q<sub>2</sub> in figure 1, is a phase splitter transistor to drive both halves of the pull up and pull down output stage. It allows the input condition to be produced in opposite phases so that the output transistors can be driven in anti-phase. This allows Q<sub>3</sub> to be on when Q<sub>4</sub> is off and vice versa as shown in figure 3. |
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| {{ :university:courses:electronics:a27_f3.png?500 |}} | {{ :university:courses:electronics:a27_f3.png?500 |}} |
| <WRAP centeralign> Figure 4 Output Stage </WRAP> | <WRAP centeralign> Figure 4 Output Stage </WRAP> |
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| The diode, D<sub>1</sub>, serves to increase the effective turn on voltage of Q<sub>4</sub> which allows it to be turned off before Q<sub>3</sub>turns fully on. This helps prevent potentially large surge currents from flowing in the output stage during transitions between logic states. Resistor R<sub>4</sub> also serves to limit the current that is allowed to flow in the output stage. The disadvantage is that the logic high voltage is reduced by an amount of the diode drop as shown in figure 6. | The diode, D<sub>1</sub>, serves to increase the effective turn on voltage of Q<sub>4</sub> which allows it to be turned off before Q<sub>3</sub>turns fully on. This helps prevent potentially large surge currents from flowing in the output stage during transitions between logic states. Resistor R<sub>4</sub> also serves to limit the current that is allowed to flow in the output stage. The disadvantage is that the logic high voltage is reduced by an amount of the diode drop as shown in figure 7. |
| ===== Materials: ===== | ===== Materials: ===== |
| ADALM2000 Active Learning Module\\ | ADALM2000 Active Learning Module\\ |
| 1 - 100 Ω Resistor\\ | 1 - 100 Ω Resistor\\ |
| 1 - small signal diode (1N914)\\ | 1 - small signal diode (1N914)\\ |
| 5 - small signal NPN transistors (2N3904 and SSM2212) | 5 - small signal NPN transistors (2N3904) |
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| =====TTL Inverter===== | =====TTL Inverter===== |
| ==== Directions: ==== | ==== Directions: ==== |
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| The NPN transistors normally supplied with your ADALP2000 Analog Parts Kit are limited to 3 2N3904 and 1 SSM2212 matched pair. The SSM2212 device cannot be used for the input device(s) Q<sub>1</sub> (a,b) because it contains internal protection diodes across the base and emitter terminals to prevent them from being reverse biased. The SSM2212 NPN pair can be used for the output stage devices Q<sub>3</sub> and Q<sub>4</sub>. Use the 3 2N3904 transistors for Q<sub>1</sub> (a,b) and Q<sub>2</sub>. | Build the circuit shown in figure 5 on your solder-less bread board. The NPN transistors supplied with your ADALP2000 Parts Kit are limited to 5 2N3904 and 1 TIP31 power transistor. Use the 5 2N3904 transistors and a 1N914 diode. |
| First, connect the TTL inverter circuit on your breadboard. | First, connect the TTL inverter circuit on your breadboard. |
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| {{ :university:courses:electronics:a27_f5a.png?550 |}} | {{ :university:courses:electronics:a27_f5a.png?550 |}} |
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| <WRAP centeralign> Figure 6 TTL Inverter Breadboard Circuit</WRAP> | <WRAP centeralign> Figure 6 TTL Inverter Breadboard Circuit</WRAP> |
| ==== Procedure: ==== | ==== Procedure: ==== |
| Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude values. Use the oscilloscope in the x-y mode to observe the voltage-transfer curve of the circuit. | Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak peak-to-peak values. Use the oscilloscope in the x-y mode to observe the voltage-transfer curve of the circuit. |
| {{ :university:courses:electronics:a27_f7.png?500 |}} | {{ :university:courses:electronics:a27_f7.png?500 |}} |
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| <WRAP centeralign> Figure 9 TTL two input NAND Gate Breadboard Circuit </WRAP> | <WRAP centeralign> Figure 9 TTL two input NAND Gate Breadboard Circuit </WRAP> |
| ==== Procedure: ==== | ==== Procedure: ==== |
| Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude values and W2, 100 Hz triangle wave with 0 V offset and 6 V amplitude values and 90° phase. Use the oscilloscope to observe the output of the circuit, CH2. | Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak values and W2, 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak values and 90° phase. Use the oscilloscope to observe the output of the circuit, CH2. |
| {{ :university:courses:electronics:a27_f10.png?550 |}} | {{ :university:courses:electronics:a27_f10.png?550 |}} |
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| <WRAP round download> | <WRAP round download> |
| *Resources:* | *Resources:* |
| * Fritzing files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/fritzing/ttl_inv_and_nand_bb | ttl_inv_and_nand_bb ]] | * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/ttl_inv_and_nand_bb | ttl_inv_and_nand_bb ]] |
| * LTspice files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/ltspice/ttl_inv_and_nand_ltspice | ttl_inv_and_nand_ltspice ]] | * LTspice files: [[downgit>education_tools/tree/master/m2k/ltspice/ttl_inv_and_nand_ltspice | ttl_inv_and_nand_ltspice ]] |
| </WRAP> | </WRAP> |
| =====For Further Reading:===== | =====For Further Reading:===== |
