Wiki

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
university:courses:electronics:electronics-lab-27 [25 Jan 2019 13:31]
Antoniu Miclaus add ltspice files
university:courses:electronics:electronics-lab-27 [23 Aug 2019 14:03]
Antoniu Miclaus
Line 57: Line 57:
 <WRAP centeralign>​ Figure 6 TTL Inverter Breadboard Circuit</​WRAP>​ <WRAP centeralign>​ Figure 6 TTL Inverter Breadboard Circuit</​WRAP>​
 ==== Procedure: ==== ==== Procedure: ====
-Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude values. Use the oscilloscope in the x-y mode to observe the voltage-transfer curve of the circuit.+Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude ​peak-to-peak peak-to-peak ​values. Use the oscilloscope in the x-y mode to observe the voltage-transfer curve of the circuit.
 {{ :​university:​courses:​electronics:​a27_f7.png?​500 |}} {{ :​university:​courses:​electronics:​a27_f7.png?​500 |}}
  
Line 74: Line 74:
 <WRAP centeralign>​ Figure 9 TTL two input NAND Gate Breadboard Circuit </​WRAP>​ <WRAP centeralign>​ Figure 9 TTL two input NAND Gate Breadboard Circuit </​WRAP>​
 ==== Procedure: ==== ==== Procedure: ====
-Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude values and W2, 100 Hz triangle wave with 0 V offset and 6 V amplitude values and 90° phase. Use the oscilloscope to observe the output of the circuit, CH2.+Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude ​peak-to-peak ​values and W2, 100 Hz triangle wave with 0 V offset and 6 V amplitude ​peak-to-peak ​values and 90° phase. Use the oscilloscope to observe the output of the circuit, CH2.
 {{ :​university:​courses:​electronics:​a27_f10.png?​550 |}} {{ :​university:​courses:​electronics:​a27_f10.png?​550 |}}
  
Line 142: Line 142:
 The output circuitry of a typical TTL logic gate is commonly referred to a totem-pole output because the two output transistors are stacked one above the other like carvings on a totem pole. Is a gate circuit with a totem-pole output stage able to source load current, sink load current, or do both? The output circuitry of a typical TTL logic gate is commonly referred to a totem-pole output because the two output transistors are stacked one above the other like carvings on a totem pole. Is a gate circuit with a totem-pole output stage able to source load current, sink load current, or do both?
  
 +<WRAP round download>​
 *Resources:​* *Resources:​*
   * Fritzing files: [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​fritzing/​ttl_inv_and_nand_bb | ttl_inv_and_nand_bb ]]   * Fritzing files: [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​fritzing/​ttl_inv_and_nand_bb | ttl_inv_and_nand_bb ]]
   * LTspice files: [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​ltspice/​ttl_inv_and_nand_ltspice | ttl_inv_and_nand_ltspice ]]   * LTspice files: [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​ltspice/​ttl_inv_and_nand_ltspice | ttl_inv_and_nand_ltspice ]]
 +</​WRAP>​
 =====For Further Reading:​===== =====For Further Reading:​=====
  
university/courses/electronics/electronics-lab-27.txt · Last modified: 25 Jun 2020 22:07 (external edit)