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| university:courses:electronics:electronics-lab-1st [26 Oct 2018 12:42] – [For further reading:] Antoniu Miclaus | university:courses:electronics:electronics-lab-1st [05 Mar 2019 10:53] – [Additional Background on settling time measurements:] Antoniu Miclaus |
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| The circuit in figure 4 works best if low capacitance Schottky diodes are used for D<sub>1</sub>, D<sub>2</sub>, D<sub>3</sub>, and the lead lengths on all the connections are minimized. A short length of 50Ω coax can be used to connect the pulse generator to the circuit, however best results are obtained if the test fixture is connected directly to the output of the generator. The pulse generator is adjusted to output a positive-going pulse at "A" which rises from approximately -1.8 V to +0.5 V in less than 5 nSec (assuming the settling time of the test device is in the order of 20 nSec). Shorter rise times may generate ringing, and longer rise times can degrade the test device settling time; therefore some optimization is required in the actual circuit to get best performance. When the pulse generator output "A" goes above 0 V, D<sub>1</sub> begins to conduct, and D<sub>2</sub>/D<sub>3</sub> are reversed biased. The "0V" region of the signal "B" at the input of the device to be tested is flat "by definition"-neglecting the leakage current and stray capacitance of the D<sub>2</sub>-D<sub>3</sub> series combination. The D<sub>1</sub> diode and its 100O resistor help maintain an approximate 50O termination during the time the pulse at "A" is positive. | The circuit in figure 4 works best if low capacitance Schottky diodes are used for D<sub>1</sub>, D<sub>2</sub>, D<sub>3</sub>, and the lead lengths on all the connections are minimized. A short length of 50Ω coax can be used to connect the pulse generator to the circuit, however best results are obtained if the test fixture is connected directly to the output of the generator. The pulse generator is adjusted to output a positive-going pulse at "A" which rises from approximately -1.8 V to +0.5 V in less than 5 nSec (assuming the settling time of the test device is in the order of 20 nSec). Shorter rise times may generate ringing, and longer rise times can degrade the test device settling time; therefore some optimization is required in the actual circuit to get best performance. When the pulse generator output "A" goes above 0 V, D<sub>1</sub> begins to conduct, and D<sub>2</sub>/D<sub>3</sub> are reversed biased. The "0V" region of the signal "B" at the input of the device to be tested is flat "by definition"-neglecting the leakage current and stray capacitance of the D<sub>2</sub>-D<sub>3</sub> series combination. The D<sub>1</sub> diode and its 100O resistor help maintain an approximate 50O termination during the time the pulse at "A" is positive. |
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| | <WRAP round download> |
| **Lab Resources:** | **Lab Resources:** |
| * Fritzing files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/fritzing/opamp_settling_time_bb | opamp_settling_time_bb]] | * Fritzing files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/fritzing/opamp_settling_time_bb | opamp_settling_time_bb]] |
| | * LTSpice files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/ltspice/opamp_settling_time_ltspice | opamp_settling_time_ltspice]] |
| | </WRAP> |
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| ==== For further reading: ==== | ==== For further reading: ==== |
