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university:courses:electronics:electronics-lab-14 [24 Sep 2019 12:31]
andreeapop [Procedure]
university:courses:electronics:electronics-lab-14 [14 Oct 2019 12:33] (current)
andreeapop [Procedure]
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 ====Procedure==== ====Procedure====
 Open Scopy and enable the positive power supply to 5V. in Pattern generator you should configure the DAC input signals according to the timing diagram of AD5626 presented in datasheet. Open Scopy and enable the positive power supply to 5V. in Pattern generator you should configure the DAC input signals according to the timing diagram of AD5626 presented in datasheet.
-Start by configuring SPI signals. Create a group channel with DIO0, DIO1 and DIO2. If the connections were done as in figure 8 then DIO0 is the clock signal, DIO2 the data signal and DIO0 the /CS signal. ​+Start by configuring SPI signals. Create a group channel with DIO0, DIO1 and DIO2. If the connections were done as in figure 8 then DIO1 is the clock signal, DIO2 the data signal and DIO0 the /CS signal
 +Pay attention that the digital channels are in the right order when grouped as SPI (see figure 11)
 It is specified in datasheet that the clock width for both high and low states should be at least 30 ns. From this you can compute the clock period and therefore maximum frequency. ​ It is specified in datasheet that the clock width for both high and low states should be at least 30 ns. From this you can compute the clock period and therefore maximum frequency. ​
 Set the clock frequency to 1Mhz. Set CLK Polarity and CLK Phase to 1.  Set the clock frequency to 1Mhz. Set CLK Polarity and CLK Phase to 1. 
university/courses/electronics/electronics-lab-14.1569321085.txt.gz · Last modified: 24 Sep 2019 12:31 by andreeapop