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The objective of this exercise is to explore the concepts of digital to analog conversion making use of the CMOS inverter as reference switches for a resistor ladder divider (used in DAC).
We will exploit the simple CMOS inverter logic gate as a pair of switches. The digital I/O signals of the ADALM2000 module can be configured as standard CMOS dividers with a +3.3 Volt supply (push-pull mode). In the simplest form, a CMOS output consists of one PMOS device, M1 and one NMOS device M2. Generally the CMOS fabrication process is designed such that the threshold voltage, VTH, of the NMOS and PMOS devices are roughly equal i.e. complementary. The designer of the inverter then adjusts the width to length ratio, W/L, of the NMOS and PMOS devices such that their respective transconductance and thus their RON, is also equal. Only one of the two transistors is ever on at the same time connecting the Output to either VDD or VSS. We can consider these two voltages to be the reference for out DAC.
Figure 1 CMOS output driver
When used in what is referred to as “voltage mode” legs the R-2R resistor ladder, figure 2, are alternately driven to either of 2 reference voltage levels based on the digital code (D0-7). Digital 0 for VREF- and digital 1 for VREF+. Depending on the digital input code VLADDER ( in figure 2 ) will be some fraction of the difference between the two reference levels. The negative of the two reference voltages (VREF-) is often ground (VSS). The positive reference voltage (VREF+) in our case here will be the positive supply (VDD) for the CMOS driver.
ADALM2000 Active Learning Module
9 - 20 KΩ Resistors
9 - 10 KΩ Resistors
1 - OP27 amplifier
Build the 8 bit resister ladder circuit shown in figure 2, preferably on your solder-less breadboard. The number of resistors normally supplied in the Analog Parts Kit is not sufficient to build the full 8 bit ladder. It is best to use 1% resistors for this project if you have access to them.
Figure 2 R-2R Resistor Ladder circuit
Connect the 8 digital outputs designated by the blue boxes, and the scope channel and AWG output designated by the green boxes to the resistor ladder circuit as shown. Remember to connect power to the op amp supply pins.
With both R1 and R2 installed, set AWG1 to a DC voltage equal to the VREF+ of the DAC which will be the +3.3 Volt supply voltage of the CMOS digital outputs. This will produce a bipolar output voltage which will swing from -3.3V to +3.3V. Disconnect AWG1 and remove resistor R1 for a unipolar output voltage which will swing from 0 to +3.3V. Start the Scopy software. Open up the Pattern Generator screen. Select and group DIO 0 - 7. Now edit the parameters. Set pattern to Binary counter. The output should be PP (for push-pull) and set the frequency for 256 KHz. You should see something that looks like the screen below shown in figure 4. Lastly, hit the Run button.
Figure 4 Pattern Generator screen
Open the Scope screen, turn channel 2 on, and set the time base for 200us/div. Be sure to hit the green Run button. You may also need to adjust the vertical range for the channel 1 V/div is probably good to start with. You should see (figure 4) the voltage ramp up from 0 volts to 3.3 volts. The period of the ramp should be 1mSec.
Figure 5 Scope screen
Change the digital pattern. Try the Random pattern and open the FFT window on the scope. You can also load custom patterns by making a plain text csv file with a column of numbers ranging from 0 to 255 (for the 8 bit wide bus). Load your custom pattern and see what happens.
Here are some pre-made waveform files you can try: Sine, Triangle, Gaussian pulse etc. waveforms_pg
AD5626 is a vltage output digital-to-analog converter that can operate from a single 5V supply. It contains the DAC, input shift register and latches, reference, and a rail to-rail output amplifier which can swing to either rail and is set to a range of 0 V to 4.095 V for a one-millivolt-per-bit resolution. This part features a serial interface that is high speed, threewire, DSP compatible with data in (SDIN), clock (SCLK), and load strobe (LDAC). There is also a chip-select pin for connecting multiple DACs. The CLR input sets the output to zero scale at power on or upon user demand.
Figure 6. functional block diagram of AD5626
The AD5626 has a separate serial input register from the 1-bit DAC register and it allows preloading of a new data value into the serial register without disturbing the present DAC output voltage. the loaded value can be transferred to the DAC register by strobing the LDAC pin.
This mode of operation is the basic mode for AD5626. You can verify the god functionality AD5626 according to the unipolar code table of the digital to analog convertor.
Figure 7. Unipolar code table of AD5626
Figure 8. Connections for Unipolar operation AD5626
Figure 9. AD5626 breadboard connections
Open Scopy and enable the positive power supply to 5V. in Pattern generator you should configure the DAC input signals according to the timing diagram of AD5626 presented in datasheet. Start by configuring SPI signals. Create a group channel with DIO0, DIO1 and DIO2. If the connections were done as in figure 8 then DIO0 is the clock signal, DIO2 the data signal and DIO0 the /CS signal. It is specified in datasheet that the clock width for both high and low states should be at least 30 ns. From this you can compute the clock period and therefore maximum frequency. Set the clock frequency to 1Mhz. Set CLK Polarity and CLK Phase to 1.
As the AD5626 is a 12-bit DAC, the data sent through SPI should be aleast 12 bits long. Set the number of Bytes per frame to 2 and it will send 16 bits when the conversion is initiated. In the Data text box you can enter the value to be sent to the ADC. The signals of the SPI group channel should resemble the timing diagram of the AD5626 digital to analog converter.
Figure 10. AD5626 SPI timing diagram
Now you should configure /LDAC and /CLR signals. From the datasheet we know that the shift register contents are updated on the rising edge of /LDAC if /CLR is high. Set the pattern of DIO4 (/CLR) as “Number” and enter the value 1. /LDAC signal(DIO3) should have a rising edge before /CS falling egde and should be high as long as bits are transmitted serially. In order to fulfill tre previoulsy stated conditions, DIO3 signal can be set at 13kHz frequency and 160 degrees phase. In figure 10 are presented all the input signals needed for AD5626 digital to analog conversion.
Figure 11. Pattern generator signals setup
The last step is to open oscilloscope and connect channel 1 to the output of AD5626. Enable channel 1 measurements and enter a value in the “Data” area of SPI. In figure 12 you can see the output voltage if the data sent through SPI is 7FF.
Figure 12. AD5626 output voltage for 7FF input.
1. Using Ohm's law and the formula for resistors in parallel, what is the output voltage of the R-2R DAC when inputs D7 and D6 are connected to each combination of ground and 3.3 volts? Please present the results as a table.
2. How much current will flow through this resistor network when input D6 is connected to 3.3 volts and D7 to ground?
3. Discuss which DAC topology had better linearity, and why you would (or would not) expect this to be the case.
4. How would you expect these DACs to perform for high frequency inputs? For better high frequency components, would you want smaller or larger resistor values? Discuss the relative merits of choosing large or small resistors for the DAC.
5. One of the effects of reducing the size of the resistors is that the parasitic switch resistances could start to become significant relative to the resistors. What would the output levels be for a 3-bit Binary-Weighted Resistor DAC where the switch resistance in figure 1 was 0.25R?
6. If you were going to design a 16-bit DAC for audio purposes (for a mp3 player output), how would the resistor tolerances affect the errors in the output for an R-2R ladder DAC?
Analog Devices Mini Tutorial 015 http://www.analog.com/static/imported-files/tutorials/MT-015.pdf
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