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university:courses:electronics:electronics-lab-14 [12 Jul 2019 13:59]
Pop Andreea [Activity 14: R-2R Resistor Ladder Digital to Analog Converter]
university:courses:electronics:electronics-lab-14 [20 Sep 2019 16:12]
Pop Andreea
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-======Activity:​ R-2R Resistor Ladder Digital to Analog Converter=====+======Activity:​Digital to analog conversion====== 
 +=====R-2R Resistor Ladder Digital to Analog Converter=====
 =====Objective:​===== =====Objective:​=====
  
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 Here are some pre-made waveform files you can try: Sine, Triangle, Gaussian pulse etc. [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​import_waveforms/​waveforms_pg | waveforms_pg]] Here are some pre-made waveform files you can try: Sine, Triangle, Gaussian pulse etc. [[ https://​minhaskamal.github.io/​DownGit/#/​home?​url=https://​github.com/​analogdevicesinc/​education_tools/​tree/​master/​m2k/​import_waveforms/​waveforms_pg | waveforms_pg]]
 +=====AD5626 12-bit nanoDAC=====
 +
 +=====Background=====
 +AD5626 is a vltage output digital-to-analog converter that can operate from a single 5V supply. ​ It contains
 +the DAC, input shift register and latches, reference, and a rail to-rail output amplifier which  can swing to either rail and is set to a
 +range of 0 V to 4.095 V for a one-millivolt-per-bit resolution.
 +This part features a serial interface that is high speed, threewire, DSP compatible with data in (SDIN), clock (SCLK), and
 +load strobe (LDAC). There is also a chip-select pin for connecting multiple DACs.
 +The CLR input sets the output to zero scale at power on or upon user demand. ​
 +
 +{{ :​university:​courses:​electronics:​functional_block_diagram_ad5626.png?​600 |}}
 +<WRAP centeralign > Figure 6. functional block diagram of AD5626 </​WRAP>​
 +
 +The AD5626 has a separate serial input register from the 1-bit DAC register and it allows preloading of a new data value into the serial register without disturbing the present DAC output voltage.
 +the loaded value can be transferred to the DAC register by strobing the LDAC pin.
 +===== Unipolar output operation=====
 +This mode of operation is the basic mode for AD5626. You can verify the god functionality AD5626 according to the unipolar code table of the digital to analog convertor.
 +
 +{{ :​university:​courses:​electronics:​unipolar_code_table.png?​400 |}}
 +<WRAP centeralign > Figure 7.  Unipolar code table of AD5626</​WRAP>​
 +===Hardware setup===
 +Connect the pins of AD5626 as shown in figure 8.
 +{{ :​university:​courses:​electronics:​connections_ad5626.png?​600 |}}
 +<WRAP centeralign > Figure 8. Connections for Unipolar operation AD5626</​WRAP>​
 +
 +{{ :​university:​courses:​electronics:​ad5626_bb_bb.png?​900 |}}
 +<WRAP centeralign > Figure 9. AD5626 breadboard connections</​WRAP>​
 +
 +
 +===Procedure===
 +Open Scopy and enable the positive power supply to 5V. in Pattern generator you should configure the DAC input signals according to the timing diagram of AD5626 presented in datasheet.
 +Start by configuring SPI signals. Create a group channel with DIO0, DIO1 and DIO2. If the connections were done as in figure 8 then DIO0 is the clock signal, DIO2 the data signal and DIO0 the /CS signal. ​
 +It is specified in datasheet that the clock width for both high and low states should be at least 30 ns. From this you can compute the clock period and therefore maximum frequency. ​
 +Set the clock frequency to 1Mhz. Set CLK Polarity and CLK Phase to 1. 
 +
 +As the AD5626 is a 12-bit DAC, the data sent through SPI should be aleast 12 bits long. Set the number of Bytes per frame to 2 and it will send 16 bits when the conversion is initiated.
 +In the Data text box you can enter the value to be sent to the ADC.
 +The signals of the SPI group channel should resemble the timing diagram of the AD5626 digital to analog converter.
 +
 +{{ :​university:​courses:​electronics:​timing_diagram.png?​900 |}} 
 +<WRAP centeralign > Figure 10. AD5626 SPI timing diagram</​WRAP>​
 +
 +Now you should configure /LDAC and /CLR signals.
 +From the datasheet we know that the shift register contents are updated on the rising edge of /LDAC if /CLR is high.
 +Set the pattern of DIO4 (/CLR) as "​Number"​ and enter the value 1. 
 +/LDAC signal(DIO3) should have a rising edge before /CS falling egde and should be high as long as bits are transmitted serially.
 +In order to fulfill tre previoulsy stated conditions, DIO3 signal can be set at 13kHz frequency and 160 degrees phase.
 +In figure 10 are presented all the input signals needed for AD5626 digital to analog conversion.
 +
 +{{ :​university:​courses:​electronics:​07ff.png?​900 |}}
 +
 +<WRAP centeralign > Figure 11. Pattern generator signals setup</​WRAP>​
 +
 +The last step is to open oscilloscope and connect channel 1 to the output of AD5626. Enable channel 1 measurements and enter a value in the "​Data"​ area of SPI.
 +In figure 12 you can see the output voltage if the data sent through SPI is 7FF.
 +
 +{{ :​university:​courses:​electronics:​vout_ad5626.png?​900 |}}
 +<WRAP centeralign > Figure 12. AD5626 output voltage for 7FF input.</​WRAP>​
  
 =====Questions:​===== =====Questions:​=====
university/courses/electronics/electronics-lab-14.txt · Last modified: 25 Jun 2020 22:07 (external edit)