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Activity 11. The Emitter follower (BJT)

Objective:

To investigate the simple NPN emitter follower amplifier also sometimes referred to as the common collector configuration.

Materials:

ADALM2000 Active Learning Module
Solder-less breadboard
Jumper wires
1 – 2.2KΩ Resistor ( RL )
1 – small signal NPN transistor ( 2N3904 Q1 )

Directions:

The breadboard connections are shown in the diagram below. The output of the arbitrary waveform generator, W1, is connected to the base terminal of Q1. Scope input 1+ (Single Ended) is also connected to W1 output. The collector terminal is connected to the positive (Vp) supply. The emitter terminal is connected to both the 2.2 KΩ load resistor and Scope input 2+ (Single Ended). The other end of the load resistor is connected to the negative (Vn) supply. To measure the input to output error, channel 2 of the scope can be used differentially by connecting 2+ to the base of Q1 and 2- to the emitter.

Figure 1 Emitter Follower

Hardware Setup:

The waveform generator should be configured for a 1 KHz Sine wave with 4 volt amplitude and 0 offset. The Single ended input of scope channel 2 (2+) is used to measure the voltage at the emitter. The Scope configured with channel 1+ connected to display the AWG generator output. When measuring the input to output error, channel 2 of the scope should be connected to display 2+ and 2- differential.

Figure 2 Emitter Follower Breadboard Circuit

Procedure:

Figure 3 Emitter Follower Waveforms

The incremental Gain (Vout / Vin) of the emitter follower should ideally be 1 but will always be slightly less than 1. The gain is generally given by the following equation:

From the equation we can see that in order to obtain a gain close to one we can either increase RL or decrease re. We also know that re is a function of IE and that as IE increases re decreases. Also from the circuit we can see that IE is related to RL and that as RL increases IE decreases. These two effects work counter to each other in the simple resistive loaded emitter follower. Thus to optimize the gain of the follower we need to explore ways to either decrease re or increase RL without effecting the other. Looking at the follower in another way, because of the inherent DC shift due to the transistor’s VBE, the difference between input and output should be constant over the intended swing. Due to the simple resistive load RL, the emitter current IE increases and decreases as the output swings up and down. We know that VBE is a (exponential) function of IE and will change approximately 18 mV (at room temperature) for a factor of 2 change in IE. In this +2V to -2V swing example the minimum IE = 2V/ 2.2KΩ or 0.91 mA to a maximum IE = 6V / 2.2KΩ or 2.7mA. This results in a 28 mV change in VBE. This observation leads us to the first possible improvement in the emitter follower. The current mirror from activity 5 is now substituted for the emitter load resistor to fix the amplifier transistor emitter current. A current mirror will sink a more or less constant current over a wide range of voltages. This more or less constant current flowing in the transistor will result in a more or less constant VBE. Viewed another way, the very high output resistance of the current source has effectively increased RL while re remains at a low value set by the current.

Additional Materials:

1 – 3.2KΩ Resistor ( use a 1KΩ in series with a 2.2KΩ )
1 – small signal NPN transistor ( Q1 2N3904)
2 – small signal NPN transistors ( Q2, Q3 SSM2212) selected for best Vbe matching

Figure 4 Improved Emitter Follower

Hardware Setup:

Figure 5 Improved Emitter Follower Breadboard Circuit

Procedure:

Figure 6 Improved Emitter Follower Waveforms

Figure 7 Input vs output error for resistor and current source load

Emitter follower output impedance

Objective:

An important aspect of the emitter follower is to provide power or current gain. That is to say drive a lower resistance (impedance) load from a higher resistance (impedance) source. Thus it is instructive to measure the emitter follower output impedance.

Materials:

1 – 4.7KΩ Resistor
1 – 10KΩ Resistor
1 – small signal NPN transistor ( Q1 2N3904)

Directions:

The circuit configuration below adds a resistor R2 to inject a test signal from AWG1 into the emitter (output) of Q1. The input, base of Q1, is grounded.

Figure 8 Output impedance test

Hardware Setup:

The waveform generator should be configured for a 1 KHz Sine wave with 2 volt amplitude with the offset set equal to minus the VBE of Q1 ( approximately -0.65V ). This injects a +/- 0.1mA (1V/10KΩ) current into Q1‘s emitter. Scope input 2+ measures the change in voltage seen at the emitter.

Figure 9 Output impedance test Breadboard Circuit

Procedure:

Figure 10 Output impedance test Waveforms

Plot the change in voltage measured at the emitter. The nominal emitter current in Q1 is (5V – 0.65) / 4.7KΩ or 925uA. We can calculate refrom this current as 26mV/925uA or 28Ω. How does this re compare to the value measured from the test data? Change the value of R1 from 4.7 KΩ to 2.2 KΩ and re-measure the output impedance of the circuit. How has it changed and why??

Low Offset Follower

All the follower circuits we have investigated so far have a built in offset of –VBE. The circuit shown next uses the VBE shift up of a PNP emitter follower to partially cancel the VBE shift down of an NPN emitter follower.

Materials:

1 – 6.8KΩ Resistor
1 – 10KΩ Resistor
1 – 0.01uF Capacitor
1 – small signal PNP transistor ( Q1 2N3906)
3 – small signal NPN transistors ( Q2, Q3, Q4 2N3904 or SSM2212)

Directions:

The breadboard connections are shown in the diagram below. The output of the function generator is connected to the base terminal of PNP transistor Q1. The collector terminal of Q1 is connected to diode connected NPN Q3 which is the input of a current mirror. The emitter terminal is connected to both resistor R1and the base terminal of NPN transistor Q2. Scope input 2+ is connected to both the emitter of Q2 and the Collector of Q4. The emitters of both Q3 and Q4 are connected to the negative ( Vn ) supply. For best matching use the SSM2212 matched NPN pair for Q3 and Q4.

Figure 11 Low offset follower

Hardware Setup:

Figure 12 Low offset follower Breadboard Circuit

The waveform generator should be configured for a 1 KHz Sine wave with 2 volt amplitude with the offset set equal to 0. Scope input channel 2 is set to 500mV / Div.

Procedure:

Figure 13 Low offset follower Waveforms

Figure 14

Figure 15

Driving a Capacitor

A problem suffered by the simple emitter follower can be seen when it drives a capacitive load. The rise time of the output can be relative fast as the emitter current is limited only by beta times the base current that can be supplied by the signal source driving the base. The fall time can be much slower and is limited by either the emitter resistor or current source.

Materials:

2 – 2.2KΩ Resistor
1 – 10KΩ Resistor
1 – 0.01uF Capacitor
3 – small signal PNP transistor (Q2, Q3, Q4 2N3906 SSM2220)
3 – small signal NPN transistors ( Q1, Q5, Q6 2N2904 SSM2212)

The circuit shown here in figure 10 uses feedback to adjust the current in the emitter follower as the current in the load changes. The current to pull the output negative can be as much as N times (the gain of the NPN mirror) the current in PNP Q3. For best matching use the SSM2220 matched PNP pair for Q3 and Q4and the SSM2212 matched NPN pair for Q5 and Q6(NPN mirror gain will be 1, add a second SSM2212 in parallel with Q5 to increase the mirror gain).

Figure 16 Balanced slew rate follower

Hardware Setup:

Figure 17 Balanced slew rate follower Breadboard Circuit

Procedure:

Figure 18 Balanced slew rate follower Waveforms

Figure 19 Balanced slew rate follower Waveforms

Figure 20

Figure 21

Figure 22

An alternate approach to improving the emitter follower is to reduce the effective re through negative feedback. Reducing re can be addressed by adding a second transistor to increase the negative feedback factor by increasing the open-loop-gain. The single transistor is replaced by a pair with 100% voltage feedback to the emitter of the first transistor. This is often referred to as a complementary feedback pair. The value of R2 is crucial to good linearity, as it sets the IC of transistor Q1, and also determines its collector loading.

Materials:

1 – 2.2KΩ Resistor
1 – 10KΩ Resistor
1 – small signal NPN transistor ( 2N3904 Q1 )
1 – small signal PNP transistor ( 2N3906 Q2 )

Figure 23 Complementary Feedback Pair Emitter Follower

Hardware Setup:

Figure 24 Complementary Feedback Pair Emitter Follower Breadboard Circuit

Procedure:

Figure 25 Complementary Feedback Pair Emitter Follower Waveforms

A minor addition to the complementary feedback pair emitter follower can provide a gain greater than 1. Resistor R3 is added between the collector of PNP Q2 and the emitter of NPN Q1. The output is now taken at the collector of Q2. The gain is approximated by the ratio of R3 to R1, Gain = (R1+R3)/R1. In this example it is about 3.2.

Materials:

2 – 1KΩ Resistors
1 – 2,2KΩ Resistor
1 – small signal NPN transistor ( 2N3904 Q1 )
1 – small signal PNP transistor ( 2N3906 Q2 )

Figure 26 Follower with gain greater than 1

Hardware Setup:

Figure 27 Follower with gain greater than 1 Breadboard Circuit

Procedure:

Figure 28 Follower with gain greater than 1 Waveforms

Figure 29

In addition to the gain (or as a result of it) the DC level of the output is shifted positive as compared to the gain of 1 version. This limits the range of input voltage where the circuit can operate as shown by the negative shift in the input DC level. The next plot normalizes out the DC offset.

Figure 30

To confirm that the gain is indeed about 3.2 the next plot divides the output by the gain and compares that to the input. In this example the actual gain is 3.16, most likely due to the resistor values not being exact.

Figure 31

Questions:

What limits the amount of gain greater than one that this circuit can produce?

What could be added to the circuit to remove / restore the DC levels at the input and output of this circuit?

What would happen if a diode connected NPN transistor were substituted for resistor R2 (2.2KΩ)?

Current Limit or Constant Current (Transistor Based)

This is a modification of the emitter follower to limit the current output. If the output stage of an amplifier is an emitter follower it may be necessary to limit the maximum current that can be supplied to the output load. Circuit:

Figure 32 Emitter Current Limit

Hardware Setup:

Figure 33 Emitter Current Limit Breadboard Circuit

Procedure:

Figure 34 Emitter Current Limit Waveforms

Where:

  1. R1 base resistor limits base current to transistor Q1.
  2. R2 current sense resistor used to sense the current and turn on transistor Q2.
  3. R3 Output Load.
  4. Q1 main transistor supplying the load current.
  5. Q2 current sense transistor.

Discussion:

The concept in this circuit is that R2 acts as current sense resistor. When the load current times R2, the sense voltage, reaches about 0.6 (for silicon transistors ) Q2 begins to conduct and increases current in R1 which limits the base drive to Q1reducing its output current. The maximum current from the circuit is reached when IL*R2 = 0.6. This circuit can be used to protect amplifiers (including push pull amplifiers.), power supplies and other circuits; or it can be used as a constant current circuit. This is not a precision circuit; however it is a simple and effective circuit.

Resources:

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university/courses/electronics/electronics-lab-11.txt · Last modified: 07 Dec 2018 13:40 by amiclaus