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university:courses:alm1k:alm-lab-scr [07 Feb 2022 15:24] Doug Mercer [Activity: Silicon Controlled Rectifiers (SCR)] |
university:courses:alm1k:alm-lab-scr [27 May 2022 21:05] Doug Mercer Spelling |
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| ====LATCH-UP==== | ====LATCH-UP==== | ||
| - | Latch-up is a potentially destructive situation in which a parasitic SCR is triggered, shorting the positive and negative supplies together. If current flow is not limited, electrical overstress will occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and wells form a four layer PNPN SCR structure when one of the two parasitic base-emitter junctions is momentarily forward biased during an overvoltage upset event. The SCR turns on and essentially causes a short between the V<sub>DD</sub> power supply and ground. | + | Latch-up is a potentially destructive situation in which a parasitic SCR is triggered, shorting the positive and negative supplies together. If current flow is not limited, electrical over-stress will occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and wells form a four layer PNPN SCR structure when one of the two parasitic base-emitter junctions is momentarily forward biased during an over-voltage upset event. The SCR turns on and essentially causes a short between the V<sub>DD</sub> power supply and ground. |
| Since all these MOS devices are located close together on the monolithic die, with appropriate external excitation, the parasitic SCR devices may turn on, a behavior common with poorly designed CMOS circuits. Figure 4 illustrates a simplified cross section showing two transistors, one PMOS and one NMOS; these could be connected together as logic gates or as an analog amplifier or switch. The parasitic bipolar transistors responsible for latch-up behavior, Q<sub>1</sub> (vertical PNP) and Q<sub>2</sub> (lateral NPN) are as indicated. | Since all these MOS devices are located close together on the monolithic die, with appropriate external excitation, the parasitic SCR devices may turn on, a behavior common with poorly designed CMOS circuits. Figure 4 illustrates a simplified cross section showing two transistors, one PMOS and one NMOS; these could be connected together as logic gates or as an analog amplifier or switch. The parasitic bipolar transistors responsible for latch-up behavior, Q<sub>1</sub> (vertical PNP) and Q<sub>2</sub> (lateral NPN) are as indicated. | ||
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| Looking back at figure 1 we note that the triggering current is injected at the base of the NPN Q2. The ON state can just as eaisily be triggered by pulling a current out of the base of the PNP transistor Q1 as shown in figure 5. | Looking back at figure 1 we note that the triggering current is injected at the base of the NPN Q2. The ON state can just as eaisily be triggered by pulling a current out of the base of the PNP transistor Q1 as shown in figure 5. | ||
| - | The Programmable unijunction transistor or PUT is a close relative of other four layer devices in the thyristor family. Its has a four layered construction just like the SCR and has three terminals named anode(A), cathode(K) and gate(G) again like the thyristors. It is often reffered to as a programmable Uni-Junction Transistor because its characteristics and parameters are similar to those of the UJT. The programmablility of typical UJT parameters like intrinsic standoff ratio (η), peak voltage(Vp) etc is made by connecting two external resistors. In a conventional UJT, the parameters like Vp, η etc are fixed by the device processing and cannot be changed by the user. The main application of programmable UJT are relaxation oscillators , thyristor triggering, pulse circuits and timing circuits. ON Semiconductor® is the only manufacturer of PUTs today. 2N6027 is the most common type number and it is available in a TO-92 plastic package. The internal block diagram and circuit symbol of PUT are shown below. | + | The Programmable unijunction transistor or PUT is a close relative of other four layer devices in the thyristor family. Its has a four layered construction just like the SCR and has three terminals named anode(A), cathode(K) and gate(G) again like the thyristors. It is often referred to as a programmable Uni-Junction Transistor because its characteristics and parameters are similar to those of the UJT. The programmability of typical UJT parameters like intrinsic standoff ratio (η), peak voltage(Vp) etc is made by connecting two external resistors. In a conventional UJT, the parameters like Vp, η etc are fixed by the device processing and cannot be changed by the user. The main application of programmable UJT are relaxation oscillators , thyristor triggering, pulse circuits and timing circuits. ON Semiconductor® is the only manufacturer of PUTs today. 2N6027 is the most common type number and it is available in a TO-92 plastic package. The internal block diagram and circuit symbol of PUT are shown below. |
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university/courses/alm1k/alm-lab-scr.txt · Last modified: 27 May 2022 21:05 by Doug Mercer