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The objective of this activity is to investigate the simple NPN noninverting emitter follower configuration in combination with the inverting common emitter configuration to provide two equal-amplitude, opposite-phase outputs.
As in all the ALM labs we use the following terminology when referring to the connections to the M1000 connector and configuring the hardware. The green shaded rectangles indicate connections to the M1000 analog I/O connector. The analog I/O channel pins are referred to as CA and CB. When configured to force voltage / measure current –V is added as in CA-V or when configured to force current / measure voltage –I is added as in CA-I. When a channel is configured in the high impedance mode to only measure voltage –H is added as CA-H. Scope traces are similarly referred to by channel and voltage / current. Such as CA-V , CB-V for the voltage waveforms and CA-I , CB-I for the current waveforms.
In this activity you will combine the common-collector configuration from this Activity with the common-emitter configuration from this Activity in the same amplifier to produce both in-phase and inverted ( 180 degree phase shifted ) outputs. From these two previous activities we know that the input to output gain of the common-collector or emitter follower is 1 if RE is much larger than rE. We also learned that the gain of the common emitter is RC/RE is -1 again if RE is much larger than rE.
ADALM1000 hardware module
2 – 1.0 KΩ Resistor ( RE and RC )
1 – small signal NPN transistor ( 2N3904 Q1 )
The breadboard connections are shown in figure 1. The single transistor combines common-emitter and emitter follower configurations to provide two equal amplitude, opposite phase outputs. By choosing RC = RE (and both much less than rE), the absolute gain to each output is 1, but the collector and emitter voltages will vary out of phase with each other. Shown here using the single (+5 V) power supply, the voltage swing from either output can nearly reach one half of the power supply p-p as the transistor operating condition varies from cutoff to saturation. Of course, the base bias voltage ( DC offset of CH-A output ) must be chosen to set the base voltage swing to be between a little more than + VBE of Q1 and one half of the power supply ( 2.5V ) + VBE.
Figure 1, Phase splitter. Outputs are 180° out of phase.
The CH A AWG generator should be configured for a 500 Hz Sine Shape with the Max value set to approximately 2.5 V + VBE and the Min value set to approximately +VBE. AWG channel A should be set to SVMI, Split I/O Mode and the AWG B channels should also be in Split I/O Mode (SVMI or Hi-Z does not matter in this case). The AIN and BIN input pins, are used to measure the voltage at the emitter or the voltage at the collector. To also display the AWG channel A output waveform we can use the X Math trace. From the Curves drop down menu select CA-V, CB-V and X Math traces. Open the Math controls screen and enter AWGAwaveform[t] in the X Math Formula entry. The Units can be V and the X Axis can be V-A.
To measure the input to output gain compare the p-p voltage measurements at the emitter and collector to the AWG A p-p setting (Max – Min). You can also display the differential voltage (DC part cancels) between the two outputs by clicking on the CBV-CAV Built In Expression on the Math controls.
Be sure to save a copy of the scope screen to be included in your lab report.
Phase splitter. Outputs at emitter and collector are 180° out of phase.
Adjust the Min and Max values of the Channel A output such that the signal seen at the emitter swings from nearly 0 V to slightly less than 2.5 V and the signal seen at the collector swings from nearly 5 V to slightly more than 2.5 V and is not clipped. The incremental Gain (Vout / Vin) of the noninverting emitter follower path and inverting path to the collector should be 1 and -1 respectively.
The DC or average values of the two output waveforms are not the same. It is often desirable to produce outputs centered on the same DC value. Next you will investigate two techniques to do this.
2 – 0.1 uF capacitors ( C1 and C2 )
2 – 10 KΩ resistors ( R1 and R2 )
2 – 1N914 small signal diodes ( D1 and D2 )
Add the two DC blocking capacitors and resistors tied to +2.5 V as shown in figure 2 to the circuit from figure 1. The capacitors remove or block the DC or average part of the signals and pass the AC part of the signals. The resistors tied to the +2.5 V supply set the new DC or average values for the signals seen at the outputs by charging the capacitors such that the outputs will be centered on +2.5 V. The value of the coupling capacitors set the circuit’s low-frequency cutoff point.
Figure 2, Outputs centered on +2.5 V
Another technique to set the DC level after the capacitors is to replace the two 10 KΩ resistors with diodes as shown in figure 3. The diodes charge the capacitors to a value such that the negative peaks of the waveforms will be clamped to a voltage equal to the forward biased voltage drop of the diodes below the +2.5 V supply.
Figure 3, Diode Clamp DC restoration
Try revering the direction of diodes D1 and D2 to see what happens. What is the new DC level?
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