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This version (10 May 2019 13:58) was approved by amiclaus.The Previously approved version (17 May 2015 19:58) is available.Diff

Activity 4M: NMOS FET characteristic curves

Objective:

The purpose of this activity is to investigate the drain current vs. gate voltage characteristics of an NMOS and PMOS FET transistors. The ADALP2000 kit of parts will contain a number of transistors, both NMOS and PMOS enhancement mode devices of various types, that can be used.

Notes:

As in all the ALM labs we use the following terminology when referring to the connections to the M1000 connector and configuring the hardware. The green shaded rectangles indicate connections to the M1000 analog I/O connector. The analog I/O channel pins are referred to as CA and CB. When configured to force voltage / measure current -V is added as in CA-V or when configured to force current / measure voltage -I is added as in CA-I. When a channel is configured in the high impedance mode to only measure voltage -H is added as CA-H.

Scope traces are similarly referred to by channel and voltage / current. Such as CA-V , CB-V for the voltage waveforms and CA-I , CB-I for the current waveforms.

NMOS ID> vs. VGS curves

Materials:

ADALM1000 hardware module
Solder-less breadboard
Jumper wires
1 - Small signal NMOS transistor (CD4007 or ZVN2110A)

NMOS device Directions:

The drain current vs. gate voltage characteristics of an NMOS transistor can be measured using the ALM1000 hardware and the following connections as shown in figure 1. Set up the breadboard with the channel A generator output attached to the gate terminal of M1. Connect the drain terminal of M1 to the channel B generator output. Connect the source terminal of M1 to ground.

Figure 1 NMOS ID vs VGS setup

Hardware Setup:

The channel A generator should be configured for a 100 Hz triangle wave with 4.5 volt Max and 1.0 volt Min. The channel B DC voltage source can be adjusted from 0 V to 5 V. The measurement channel CB-I measures the current in the drain of transistor.

Procedure:

Load the captured data in to spreadsheet or other analysis software. Plot the drain current vs. the gate voltage of the transistor (VGS) for various DC voltages on the drain. No drain current should flow when VGS is less than VTHthe threshold voltage of the transistor. The threshold voltage, VTH, can be both positive, for an enhancement mode, and negative, for a depletion mode device. When VGS is greater than VTH, the gate voltage to drain current relationship is quadratic. Now plot the drain current vs. the square of the gate voltage. The line should be approximately straight.

Future activities will rely on matching of the threshold voltage, VTH, of at least two FETs. You should record the VTHfor each device you have available and sort them by their threshold voltages.

Questions:

Insert further questions here.

NMOS ID vs. VDS curves

Objective:

The purpose of this activity is to investigate the drain current ID vs. drain to source voltage VDS characteristic curves of an NMOS FET transistor.

Materials:

1 - Small signal NMOS transistor (CD4007 or ZVN2110A)

NMOS Directions:

Starting with the previous breadboard setup, Move the CA-V triangle wave generator drain of the transistor. Now place CV-B generator on the gate terminal.

Figure 2 NMOS ID vs VDS setup

Hardware Setup:

The setup is the same as the previous experiment except now measurement channel CA-I is set to display the transistor IDS. The drain voltage is swept using a 5 volt Max, 0 V Min triangle wave. VDS is measured by CA-V.

A stair-step waveform will be needed to drive the gate of the transistor. Set the Channel B generator output to the 10 level stair-step waveform. Set the frequency to 20Hz, the Max to 4.25 V and the Min to 1.25 V. The extra 1.25 volts is an initial estimate of VTH. The waveform in the display should start at 1.25 V and increase in 0.3 V increments to 4.25 V. Set the channel A generator to a triangle wave with a Max of 5.0 V and a Min of 0 V (wave should swing from 0 to 5V). Set the frequency to 200 Hz ( 10 times the 20 Hz of channel B). Comparing the waveforms in channel A and channel B, the triangle wave in channel A should go through one cycle from 0 to 5 V and back to zero during the time of one step in the waveform in channel B. Adjust the phases of channel A and/or channel B to make them line up in this way if they do not.

Procedure:

Once the VTH of the device is known from the previous measurement, the starting offset for the stair step waveform used on the gate, from generator CB-V, can be established. The height of the steps should be set, or adjusted according to the gain (mA/V2) of the transistor being measured. This can also be gotten from the previous ID vs. VGS data.

Questions:

Insert further questions here.

PMOS ID vs. VGS curves

Materials:

ADALM1000 hardware module
Solder-less breadboard
Jumper wires
1 - Small signal PMOS transistor (CD4007 or ZVP2110A)

PMOS device Directions:

The drain current vs. gate voltage characteristics of a PMOS transistor can be measured using the ALM1000 hardware. To measure the PMOS device, alter the characteristic curve measurement circuit as shown in figure 3. The connections are not very different from those in figure 1 but the polarity of the voltage waveforms generated by channel A and channel B must now be negative with respect to the PMOS source. To accommodate this the source is now connected to +5 V. Set up the breadboard with the channel A generator output attached to the gate terminal of M1. Connect the drain terminal of M1 to the channel B generator output.

Figure 3 PMOS ID vs VGS setup

You can use the same step staircase waveform you used for the NMOS device to drive the gate voltage for the PMOS device. However, you will need to set the Max to +5 V - VTH or 3.8 V and set the Min to 0.8 V. The waveform in the display should now start at 3.8 V and decrease in 0.3 V increments to 0.8 V.

Hardware Setup:

The channel A generator should be configured for a 100 Hz triangle wave with 3.5 volt Max and 1.0 volt Min. The channel B DC voltage source can be adjusted from 0 V to 5 V. The measurement channel CB-I measures the current in the drain of transistor.

Procedure:

Load the captured data in to spreadsheet or other analysis software. Plot the drain current vs. the gate voltage of the transistor (VGS) for various DC voltages on the drain. No drain current should flow when VGS is less than VTHthe threshold voltage of the transistor. The threshold voltage, VTH, can be both positive, for an enhancement mode, and negative, for a depletion mode device. When VGS is greater than VTH, the gate voltage to drain current relationship is quadratic. Now plot the drain current vs. the square of the gate voltage. The line should be approximately straight.

Future activities will rely on matching of the threshold voltage, VTH, of at least two FETs. You should record the VTHfor each device you have available and sort them by their threshold voltages.

Questions:

Insert further questions here.

PMOS ID vs. VDS curves

Objective:

The purpose of this activity is to investigate the drain current ID vs. drain to source voltage VDS characteristic curves of an PMOS FET transistor.

Materials:

1 - Small signal PMOS transistor (CD4007 or ZVP2110A)

PMOS Directions:

Starting with the previous breadboard setup, Move the CA-V triangle wave generator drain of the transistor. Now place CV-B generator on the gate terminal.

Figure 4 PMOS ID vs VDS setup

Hardware Setup:

The setup is the same as the previous experiment except now measurement channel CA-I is set to display the transistor IDS. The drain voltage is swept using a 5 volt Max, 0 V Min triangle wave channel B generator. VDS is measured by CA-V.

A stair-step waveform will be needed to drive the gate of the transistor. Set the Channel B generator output to the 10 level stair-step waveform. Set the frequency to 20Hz, the Max to 4.25 V and the Min to 1.25 V. The extra 1.25 volts is an initial estimate of VTH. The waveform in the display should start at 1.25 V and increase in 0.3 V increments to 4.25 V. Set the channel A generator to a triangle wave with a Max of 5.0 V and a Min of 0 V (wave should swing from 0 to 5V). Set the frequency to 200 Hz ( 10 times the 20 Hz of channel B). Comparing the waveforms in channel A and channel B, the triangle wave in channel A should go through one cycle from 0 to 5 V and back to zero during the time of one step in the waveform in channel B. Adjust the phases of channel A and/or channel B to make them line up in this way if they do not.

Procedure:

Once the VTH of the device is known from the previous measurement, the starting offset for the stair step waveform used on the gate, from generator CB-V, can be established. The height of the steps should be set, or adjusted according to the gain (mA/V2) of the transistor being measured. This can also be gotten from the previous ID vs. VGS data.

Questions:

Insert further questions here.

Resources:

For Further Reading:

http://en.wikipedia.org/wiki/MOSFET

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university/courses/alm1k/alm-lab-4m.txt · Last modified: 10 May 2019 13:58 by amiclaus