The objective of this lab activity is to examine active rectifier circuits. Specifically one that combines an op amp, a low-threshold P-channel MOSFET, and feedback to synthesize a one way current valve or rectifier with less forward drop than a conventional PN junction diode.
As in all the ALM labs we use the following terminology when referring to the connections to the M1000 connector and configuring the hardware. The green shaded rectangles indicate connections to the M1000 analog I/O connector. The analog I/O channel pins are referred to as CA and CB. When configured to force voltage / measure current –V is added as in CA-V or when configured to force current / measure voltage –I is added as in CA-I. When a channel is configured in the high impedance mode to only measure voltage –H is added as CA-H.
Scope traces are similarly referred to by channel and voltage / current. Such as CA-V, CB-V for the voltage waveforms and CA-I , CB-I for the current waveforms.
Power supplies that use conventional diodes to rectify an AC voltage to obtain a DC voltage must deal with certain inherent inefficiencies. A standard diode or ultra-fast diode can have a 1 V forward voltage or higher at its rated current. This forward drop of the diode is in series with the AC power source which lowers the potential DC output voltage. In addition this drop in voltage times the current supplied through the diode can represent significant power dissipation and heat generation.
The lower forward voltage of Schottky diodes is an improvement over a standard diode. But Schottky diodes also have a built in fixed forward voltage. Higher efficiencies can be achieved by actively switching MOSFET devices synchronously with the input AC waveform to emulate diodes, taking advantage of the FET's lower conduction losses. Active rectification, also often referred to as Synchronous rectification, means switching the FET device on and off at an appropriate point in the AC waveform according to the polarity, so it acts as a rectifier conducting current only in the desired direction.
Unlike the situation with the junction diode, conduction losses depend upon ON resistance (RDS(ON)) and current. Choosing a large enough FET with a low RDS(ON) reduces the forward voltage drop to a fraction of what any diode can achieve. Hence, the synchronous rectifier will have a much lower loss than a diode, helping improve the overall efficiency.
Having to synchronize the gate signal used to turn on and off the FET complicates the circuit design over diode based rectifiers. This complexity is often a better alternative to the added complexity caused by having to remove the heat generated by the diodes. With ever increasing efficiency requirements, there is often no better alternative than to use synchronous rectification.
ADALM1000 hardware module
Solder-less Breadboard and jumper wire kit
1 – AD8542 dual or AD8541 single CMOS op amp with rail-to-rail input/output
1 – ZVP2110A PMOS transistor ( or equivalent )
1 - 4.7 uF capacitor
1 - 220 uF capacitor
1 – 2.2 KΩ resistor
1 – 47 KΩ resistor
1 – 1 MΩ resistor
Build the simple half wave rectifier circuit shown in figure 1 on your solder-less breadboard. An active gate drive circuit, such as shown in the figure, uses an op-amp (AD8541/2) to sense when the AC input waveform, from the output of the channel A voltage generator, CA-V is more positive than the output voltage, VOUT, and turn on the PMOS transistor, M1. The circuit provides active rectification for AC voltages as low as the minimum power supply voltage for the op-amp (2.7 volts for the AD8541/2) or the gate threshold voltage of the PMOS device (typically 1.5 V for the ZVP2110A). At lower input voltages, the MOSFET's back-gate to drain diode takes over as an ordinary diode rectifier.
Figure 1 Active half wave rectifier with self-powered op amp
Figure 2, ZVP2110A pinout
The op-amp will turn on the PMOS transistor when VIN is more positive than VOUT according to the following equation:
where: (voltages with respect to ground)
VGATE is the voltage at the gate of M1
VIN is the AC input voltage
VOUT is the output voltage at C1and RL
You can relate the input and the output voltages to the PMOS's drain-to-source, VDS, and gate-to-source voltage, VGS, according to the following equation:
We can combine these equations to relate the MOSFET's gate drive to a function of the drain-to-source voltage:
If the value of R2 is 21 times larger in value than R1, (1MΩ / 47KΩ), a +75 mV drop across the M1's drain-to-source voltage, VDS, is sufficient to turn on the PMOS trnasistor with a threshold voltage of -1.5 V. Larger ratios of R2 to R1 could be used to either lower the input to output voltage drop or to accommodate transistors with higher threshold voltages.
The op amp is powered from the output smoothing capacitor C1 so no additional power supply is necessary. There are certain requirements for the op-amp chosen for this circuit. The amplifier must have rail-to-rail inputs and outputs and demonstrate no phase inversion of the gain when operated near the power supply rails. The op amp's bandwidth limits the frequency response of the circuit. Low supply current op amps are often chosen for this application for efficiency which generally results in low bandwidths and slew rates. At higher AC input frequencies, perhaps higher than 500 Hz, the amplifier's gain will begin to decline. The AD8541/2 single supply CMOS op amp has all of these requirements and a small supply current of only 45 uA.
AWG CHA is connected as VIN and should be configured as a sine wave with Max set to 5.0 and Min set to 0 and a frequency of 100 Hz. The channel B input, in Hi-Z mode, is used to monitor various points around the circuit such as VIN, VOUT, and the gate of M1. The CHA current trace can be used to monitor the input current waveform.
Start by using the large value 220 uF capacitor for C1. The 220 uF and 4.7 uF capacitors are polarized so be sure to connect the positive and negative terminals to your circuit correctly.
Use the CHA and CHB traces to monitor the input AC waveform at VIN and the DC output wave form at VOUT. VOUT should be very close to the peak value of VIN. Now replace the large 220 uF capacitor with the much smaller 4.7 uF capacitor. Observe the change in the waveform seen at VOUT. When is VOUT closest in value to VIN ? Compare that interval of the AC input cycle with the voltage at the gate of transistor M1.
Use the CHA current trace Measure features to obtain the peak and average value of the current. Compare the average value with the DC current in the 2.2 KΩ load resistor RL you calculate based on the voltage you measure at VOUT. Repeat this measurement for both the 220 uF and 4.7 uF capacitor values. How do the peak and average values compare between these two capacitor values?
Change the Max amplitude of the AC input waveform. What is the minimum peak value of the AC input where the PMOS transistor is still actively rectifying the input, i.e. the VGS is greater than the threshold voltage and the device is turned on? What determines this minimum voltage?
Try different frequencies for the AC input. How does the frequency affect the peak value and the width of the current pulse in RS?
Try different wave shapes for the AC input other than a sine wave, such triangle, square and trapezoid waves. How does this alter the peak and average current flowing through RS?
There are other potential uses for a circuit that essentially allows current flow in only one direction with very low voltage drop across the switch. In battery chargers, where the input power source might be intermittent such as a solar panel or wind turbine generator, it is necessary to prevent the battery from discharging when the input power source is not generating a high enough voltage to charge the battery. Generally a simple Schottky diode is used for this purpose but as was pointed out in the background section this can lead to losses in efficiency. If an op amp with sufficiently low operating supply current is employed this can often be lower than the reverse leakage current in a large Schottky diode.
The op-amp that is being used in the first example circuit to compare the input and output sides of the rectifier can replaced by discrete transistors as shown in this next example circuit, figure 3. The simple diode based half wave rectifier circuit is shown for comparison. Two PNP transistors are configured as a current mirror but with the PMOS “rectifier” transistor between the emitters. As we know from our study of the current mirror, the current in the two transistors will be equal if their VBE voltages are the same. If the voltage on the emitter of Q2, Vout, is higher than the voltage on the emitter of Q1, Vin, more current will flow in Q2. At some point the current in Q2 is large enough to pull up in the gate of PMOS device M1 turning it off. Conversely, if Vin is equal to or greater than Vout Q2 will not have enough current to pull Vgate high, or be completely turned off. Note that for the case where Vin is equal to Vout the current in both PNP transistors will be equal and equal to Vin-VBE/R1. Because R1 is larger than R2 the voltage on Vgate will be smaller, that closer to ground turning on M1.
Figure 3, PMOS/PNP based active rectifier
Just as in the op-amp based example there are limitations on the lowest voltage the circuit can operate at. As before, the minimum voltage is set by the threshold voltage of PMOS transistor M1. The maximum voltage difference between Vout and Vin (when M1 is off) is determined by the reverse breakdown voltage of Q1's emitter base junction. The difference voltage between Vout and Vin appears across the series combination of Q2's emitter-base and Q1's emitter base. Q2 will be forward biased and Q1 will be reverse biased. The emitter base reverse breakdown voltage for the 2N3906 devices used here is around 7 or 8 volts. For higher voltage designs transistors with much higher breakdown voltages will need to be chosen.
Another consideration when using this circuit is the speed at which M1 can be turned on and off. The fall time of Vgate is nominally set by the resistance value of R2 and the gate capacitance of M1. The gate capacitance can be large for high current MOS devices. The rise time of Vgate is largely set by maximum possible current that Q2 can deliver. To a large extent this is set by the beta of Q2 and the amount of available base current. The base current in Q2 is set by the value of R1 and the output voltage Vout. The pull up current from Q2 will in most cases be large enough to turn off M1 quickly, the turn on time will generally be the slower of the two times.