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- 2channel_cpack_1.svg
- 19 Jun 2017 11:09
- 46.6 KB
- 2channel_upack_4.svg
- 06 Apr 2017 15:33
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- 3channel_cpack_1.svg
- 19 Jun 2017 11:09
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- 3channel_upack_4.svg
- 06 Apr 2017 15:33
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- 4channel_cpack_1.svg
- 19 Jun 2017 11:09
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- 4channel_upack_4.svg
- 06 Apr 2017 15:33
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- 7s_encoding_clocking.jpg
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- 19 Feb 2019 14:15
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- 7s_wizard_encoding_clocking.jpg
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- 19 Feb 2019 14:17
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- 7s_wizard_init.jpg
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- 19 Feb 2019 16:36
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- 7s_wizard_linerate.jpg
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- 19 Feb 2019 14:13
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- ad463x_echo_hdl.svg
- 02 Feb 2021 13:30
- 104.8 KB
- ad463x_hdl.svg
- 02 Feb 2021 12:46
- 98.8 KB
- ad469x_hdl.svg
- 20 Oct 2020 16:33
- 92.5 KB
- ad469x_hdl1.svg
- 20 Oct 2020 16:34
- 92.5 KB
- ad713x_data_interface.svg
- 22 Mar 2018 16:35
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- ad9083_evb_2.svg
- 09 Mar 2021 16:16
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- ad9671.svg
- 02 Mar 2017 13:50
- 56.1 KB
- ad9684.svg
- 01 Mar 2017 09:23
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- ad9695_eval_setup.jpg
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- 21 Jan 2021 10:30
- 4.1 MB
- ad9695_fmc_8.svg
- 24 Feb 2021 09:14
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- ad9695_fmc_clocking_0.svg
- 19 Jan 2021 13:27
- 21.8 KB
- ad_dds_1.svg
- 04 Feb 2021 19:55
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- ad_ip_jesd204_transport_adc.png
- 782×477
- 23 Feb 2018 15:26
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- ad_ip_jesd204_transport_dac.png
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- 23 Feb 2018 15:26
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- adc_datapath_01.svg
- 07 Mar 2017 10:13
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- adc_fifo_write.svg
- 19 Feb 2015 18:28
- 75.1 KB
- adc_jesd.svg
- 02 Mar 2017 11:30
- 14.8 KB
- adc_lvds_1.svg
- 09 Aug 2016 15:55
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- adc_regmap_01.svg
- 07 Mar 2017 11:40
- 12.4 KB
- adrv9371_1.svg
- 21 Oct 2016 10:35
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- adrv9371_2.svg
- 16 Mar 2018 09:51
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- adrv9371_3.svg
- 16 Mar 2018 09:52
- 158.2 KB
- axi_ad7616_par.svg
- 30 Jun 2016 10:37
- 20 KB
- axi_ad7616_par_v2.svg
- 02 Aug 2016 13:43
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- axi_ad7616_ser.svg
- 30 Jun 2016 10:37
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- axi_ad7616_ser_v2.svg
- 02 Aug 2016 13:43
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- axi_ad9144.svg
- 01 Mar 2017 13:21
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- axi_ad9265.png
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- 21 Jul 2016 09:54
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- axi_ad9265_3.svg
- 09 Aug 2016 15:54
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- axi_ad9265_4.svg
- 16 Aug 2016 10:33
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- axi_ad9361_1.svg
- 15 Nov 2016 11:34
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- axi_ad9361_2.svg
- 15 Nov 2016 11:37
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- axi_ad9361_3.svg
- 27 Jun 2017 10:00
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- axi_ad9371_2.svg
- 16 Mar 2018 09:40
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- axi_ad9467.svg
- 02 Mar 2017 10:42
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- axi_ad9467_1.svg
- 02 Mar 2017 10:43
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- axi_ad9643.svg
- 28 Feb 2017 16:11
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- axi_ad9963.svg
- 15 May 2017 15:03
- 69.2 KB
- axi_adc_decimate.svg
- 24 Aug 2017 10:22
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- axi_adc_trigger.svg
- 29 May 2017 10:06
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- axi_adc_trigger_diagram.png
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- 01 Sep 2020 07:47
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- axi_clkgen.svg
- 07 Jul 2017 14:56
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- axi_clkgen_1.svg
- 07 Jul 2017 14:59
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- axi_dac_interpolate.svg
- 24 Aug 2017 10:24
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- axi_dmac_block_diagram.png
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- 25 Feb 2018 11:06
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- axi_dmac_block_diagram.svg
- 30 Aug 2017 12:52
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- axi_fan_control_1.svg
- 22 Mar 2019 17:23
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- axi_fan_control_pvm_vs_temp.svg
- 27 Mar 2019 10:21
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- axi_logic_analyzer.svg
- 29 May 2017 09:09
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- axi_logic_analyzer_diagram.png
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- 04 Sep 2020 12:23
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- axi_logic_analyzer_trigger.png
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- 04 Sep 2020 12:34
- 135.9 KB
- axi_pulse_gen.svg
- 01 Mar 2021 14:19
- 58.7 KB
- base_platform.svg
- 02 Sep 2016 17:23
- 131.3 KB
- base_platform_11.svg
- 09 Sep 2016 14:18
- 136.3 KB
- base_platform_12.svg
- 09 Sep 2016 14:20
- 136.3 KB
- dac_datapath.svg
- 03 Nov 2017 11:05
- 19.5 KB
- dac_fifo_read.svg
- 19 Feb 2015 18:28
- 76.4 KB
- dac_jesd.svg
- 01 Mar 2017 12:12
- 15.1 KB
- dac_regmap.svg
- 10 Nov 2017 08:18
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- dds_basic.svg
- 04 Feb 2021 19:54
- 51 KB
- dds_clk_ratio_4.svg
- 04 Feb 2021 19:55
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- dds_dual_tone.svg
- 04 Feb 2021 19:55
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- dds_in_dac_core.svg
- 04 Feb 2021 19:57
- 114.5 KB
- fmcomms11_bd.svg
- 30 May 2019 15:09
- 194.9 KB
- fw_sync_basics.svg
- 04 Feb 2021 19:55
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- fw_sync_timing.png
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- 05 Feb 2021 15:51
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- hdl_adc_interface.jpg
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- 24 Nov 2014 20:11
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- hdl_cygwin_1.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_2.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_3.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_4.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_5.png
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- 24 Feb 2017 17:31
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- hdl_dac_interface.jpg
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- 05 Sep 2014 22:37
- 261 KB
- pcore_architecture.jpg
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- 20 Oct 2014 20:04
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- pcore_bd.jpg
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- 12 Sep 2014 18:32
- 256.8 KB
- pcore_jesd.jpg
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- 24 Nov 2014 21:31
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- pulse_gen_external_sync.png
- 1300×246
- 01 Mar 2021 09:26
- 26.7 KB
- pulse_gen_load_config.png
- 1280×366
- 01 Mar 2021 09:26
- 47.3 KB
- rfifo_hdl_1.svg
- 07 Nov 2017 09:15
- 83.4 KB
- small_slave_big_master.svg
- 09 Mar 2021 14:38
- 13.8 KB
- source_sync_if_1.svg
- 23 Oct 2017 15:46
- 22.1 KB
- sysid1.svg
- 02 Oct 2019 12:12
- 12.7 KB
- ultras_initial.jpg
- 1374×964
- 21 Feb 2019 08:36
- 159.3 KB
- ultras_structural.jpg
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- 21 Feb 2019 08:41
- 55 KB
- up_if_2.svg
- 20 Jun 2017 14:23
- 228.6 KB
![[root]](/resources/tools-software/uc-drivers/microchip/ad5160?ns=&tab_files=files&do=media&tab_details=view&image=resources%3Aaf10_loadreg.png){kind=link}
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- Date:
- 16 Dec 2013 22:20
- Filename:
- af10_loadreg.png
- Format:
- PNG
- Size:
- 60KB
- Width:
- 2817
- Height:
- 1845
- References for:
- Using the ADP1051 Eighth Brick Power Module Reference Design
resources/tools-software/uc-drivers/microchip/ad5160.txt · Last modified: 04 Jul 2013 16:41 by Lucian Sin