This is an old revision of the document!
The ADF4377 is a high performance, ultralow jitter, dual output integer-N PLL with integrated VCO ideally suited for data converter MxFE clock applications. The high performance PLL has a figure of merit of -239dBc/Hz, ultralow 1/f Noise and a high PFD frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4377's fundamental VCO and output divider generate frequencies from 800 MHz to 12.8 GHz.
The ADF4377 integrates all necessary power supply bypass capacitors, saving board space on compact boards.
For multiple data converter and MxFE clock applications, the ADF4377 simplifies clock alignment and calibration routines required with other clock solutions, by implementing:
These features allow for predictable and precise multi-chip clock and SYSREF alignment. JESD204B and JESD204C subclass 1 solutions are supported by pairing the ADF4377 with an IC that distributes pairs of reference wnd SYSREF signals.
The driver contains two parts:
The Communication Driver has a standard interface, so the ADF4377 driver can be used exactly as it is provided.
The Communication Drivers must include the SPI transmission methods and GPIO control methods.
For the SPI method, the ADF4377 driver calls three functions:
For the GPIO control methods, the ADF4377 driver calls three functions:
Source code documentation for the driver is automatically generated using the Doxygen tool and it is available at: