This version is outdated by a newer approved version.
This version (22 Apr 2022 05:22) was approved by Clarence MAYOTT.The Previously approved version (21 Apr 2022 18:42) is available.
This version (22 Apr 2022 05:22) was approved by Clarence MAYOTT.The Previously approved version (21 Apr 2022 18:42) is available.This is an old revision of the document!
Table of Contents
AD4630/AD4030 - No-OS Driver
Supported Devices
Evaluation Boards
Overview
The AD4630-24 is a two-channel, simultaneous sampling, Easy Drive, 2 MSPS successive approximation register (SAR) analog-to-digital converter (ADC). The AD4030-24 is the single channel version. With a guaranteed maximum ±0.9 ppm INL and no missing codes at 24-bits, the AD4630-24 and AD4030-24 achieve unparalleled precision from −40°C to +125°C.
A low-drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4630-24 offers a typical dynamic range of 106 dB when using a 5 V reference. The AD4030-24 offers a typical dynamic range of 109dB using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 153 dB and 155.5dB for the AD4030. The wide differential input and common mode ranges allow inputs to use the full ±VREF range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4630-24 and AD4030-24. Both single-ended and differential signals are supported.
The versatile Flexi-SPI serial interface eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional DDR data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS. Echo clock mode and ADC master clock mode relax the timing requirements and simplify the use of digital isolators.
The AD4630-24's and AD4030-24's BGA package integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.
Applications:
- Automatic test equipment
- Digital control loops
- Medical instrumentation
- Seismology
- Semiconductor manufacturing
- Scientific instrumentation
Driver Description
The driver contains two parts:
- The Communication Drivers, where the specific communication functions for the desired type of processor and communication protocol have to be implemented. This driver implements the communication with the device and hides the actual details of the communication protocol to the ADI driver.
The Communication Driver has a standard interface, so the AD4630-24 driver can be used exactly as it is provided.
The Communication Driver must include SPI transmission methods and GPIO control methods.
For the SPI method, the AD4630-24/AD4030-24 driver calls three functions:
- spi_init() - initializes the SPI communication peripheral.
- spi_remove() – frees memory allocated by the SPI communication driver.
- spi_write_and_read() – conduct information transfer with the device.
For the GPIO control methods, the AD4630-24/AD4030-24 driver calls four functions:
- gpio_get_optional() - initialize GPIO peripheral and allocate memory for one GPIO control.
- gpio_remove() - frees memory allocated by the GPIO control driver.
- gpio_direction_output() - set GPIO as output.
- gpio_set_value() - set GPIO to high/low state.
Code Documentation
Source code documentation for the driver is automatically generated using the Doxygen tool and it is available at:
Downloads
resources/tools-software/uc-drivers/ad463x.1650597718.txt.gz · Last modified: 22 Apr 2022 05:21 by Clarence MAYOTT