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This version (21 Jun 2012 21:53) was approved by William Jahn.The Previously approved version (21 Jun 2012 21:00) is available.
This version (21 Jun 2012 21:53) was approved by William Jahn.The Previously approved version (21 Jun 2012 21:00) is available.This is an old revision of the document!
Multi-Tap Voltage Controlled Delay
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| The Multi-Tap Voltage Controlled Delay cell provides a variable delay to a single audio input, producing multiple outputs. Each output signal is called a “tap.” The amount of delay for each tap can be modified in real-time by updating the value on the corresponding control input pin. |  |
Input Pins
| Name | Format [int/dec] - [control/audio] | Function Description |
|---|---|---|
| Pin 0: Audio Input | decimal - audio | Audio Input signal |
| Pin 1: Variable Delay (Tap 0) | integer - control | Delay amount for output 0 (in samples) |
| … | … | … |
| Pin n: Variable Delay (Tap n-1) | integer - control | Delay amount for output n-1 (in samples) |
Output Pins
| Name | Format [int/dec] - [control/audio] | Function Description |
|---|---|---|
| Pin 0: Audio Output 0 | decimal - audio | Delayed output signal 0 |
| … | … | … |
| Pin n: Audio Output n | decimal - audio | Delayed output signal n |
GUI Controls
| GUI Control Name | Default Value | Range | Function Description |
|---|---|---|---|
| Max | 1 | Depends on size of data RAM | Controls the maximum amount of delay that can be used for each output tap. |
DSP Parameter Information
| GUI Name | Compiler Name | Function Description |
|---|---|---|
| Max | VoltageControlledDelay1940NoZipAlgwLimit1buffersize | The maximum delay (in samples) for each delay tap |
Algorithm Description
The multi-tap voltage controlled delay allows a single signal to be output as multiple, independently-delayed copies. By right-clicking and selecting the “grow” option, the user can increase the number of copies, or “taps”, to be output. A maximum of 16 taps is allowed per cell.
A delay “pool” size is chosen prior to compilation; this value will determine the amount of modulo data RAM that the compiler will attempt to reserve for each tap. The delay pool size is controlled by the drop-down menu in the middle of the cell. The equivalent delay in milliseconds is displayed below this menu. The calculation for the equivalent delay is based on the cell’s sample rate setting. Note that this delay pool size is reserved for each tap. It is not a shared pool that can be used by individual taps.
If the control input for any tap exceeds the maximum allowable delay for that tap, then the maximum value will be used.
Care must be taken so that the control inputs never go below zero (integer). If the control input a negative number, the output of the algorithm will jump to -1 (decimal).
As a simple example, a single tap can be used to delay an input signal. The example below shows three signals: input, output, and control signals. The output is a delayed copy of the input, and the control signal determines how much delay is used. In this example, 100 samples of delay is used.
If multiple taps are used, then the delay for each output will be determined separately, based on its corresponding control input pin. In the example below, Output 0 is delayed by 40 samples and Output 1 is delayed by 80 samples.
The delay can be modified in real-time, but this will cause frequency distortion on the output. If delay needs to be modified in real-time, then muting the audio when changing the delay length can help to avoid distortion. Also, changing the delay length gradually can help to mitigate the severity of the frequency distortion. An example of extreme frequency warping is shown below.
Example
The following schematic image shows the Multi Tap Voltage Controlled Delay being used with a sine tone generator as an input and two delay taps. The maximum delay is 40 samples. Output 0 is delayed by 20 samples and Output 1 is delayed by 40 samples. The schematic below additionally uses the Sine Tone, DC Source, and Output cells.
Algorithm Details
| Toolbox Path | Basic DSP – DSP Functions – Multi-Tap Voltage Controlled Delay |
| Cores Supported | AD1940 ADAU170x ADAU144x ADAU176x ADAU178x |
| “Grow Algorithm” Supported | yes - see Algorithm Growth Information |
| “Add Algorithm” Supported | no |
| Subroutine/Loop Based | no |
| Program RAM | 16* |
| Data RAM | 4** |
| Parameter RAM | 1 |
resources/tools-software/sigmastudio/toolbox/basicdsp/multitapvoltagecontrolleddelay.1340308381.txt.gz · Last modified: 21 Jun 2012 21:53 by William Jahn