Differences
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| Both sides previous revisionPrevious revision | |
| resources:tools-software:linux-drivers:iio-transceiver:adrv9009-customization [26 Jul 2019 10:44] – [ARM GPIO Settings] Michael Hennerich | resources:tools-software:linux-drivers:iio-transceiver:adrv9009-customization [30 Apr 2020 10:05] (current) – [Clocks] Michael Hennerich |
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| | adi,dig-clocks-device-clock_khz | 245760 | CLKPLL and device reference clock frequency in kHz | | | adi,dig-clocks-device-clock_khz | 245760 | CLKPLL and device reference clock frequency in kHz | |
| | adi,dig-clocks-clk-pll-vco-freq_khz | 9830400 | CLKPLL VCO frequency in kHz | | | adi,dig-clocks-clk-pll-vco-freq_khz | 9830400 | CLKPLL VCO frequency in kHz | |
| | adi,dig-clocks-clk-pll-hs-div | 1 | CLKPLL high speed clock divider | | | adi,dig-clocks-clk-pll-hs-div | 1 | CLKPLL high speed clock divider (Encoding is: VAL=Clock Divide Ratio; 0=2.0, 1=2.5, 2=3.0, 3=4.0, 4=5.0) | |
| | adi,dig-clocks-rf-pll-use-external-lo | 0 | 1= Use external LO input for RF PLL, 0 = use internal LO generation for RF PLL | | | adi,dig-clocks-rf-pll-use-external-lo | 0 | 1= Use external LO input for RF PLL, 0 = use internal LO generation for RF PLL | |
| | adi,dig-clocks-rf-pll-phase-sync-mode | 0 | Set RF PLL phase synchronization mode. Adds extra time to lock RF PLL when PLL frequency changed. See enum for options | | | adi,dig-clocks-rf-pll-phase-sync-mode | 0 | Set RF PLL phase synchronization mode. Adds extra time to lock RF PLL when PLL frequency changed. See enum for options | |
