The AD9528 is a two-stage PLL with an integrated JESD204B SYSREF generator for multiple device synchronization.
The first stage PLL (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices
The AD9528 generates two outputs (Output 1 and Output 2) with a maximum frequency of 1.25 GHz, and 12 outputs up to 1 GHz. Each output can be configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs.
Please see also here: Changing the VCXO frequency
Source | Mainlined? |
---|---|
drivers/iio/frequency/ad9528.c | No |
Function | File |
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driver | drivers/iio/frequency/ad9528.c |
include | include/linux/iio/frequency/ad9528.h |
include | include/dt-bindings/iio/frequency/ad9528.h |
Configure kernel with “make menuconfig” (alternatively use “make xconfig” or “make qconfig”)
The AD9528 Driver depends on CONFIG_SPI
Linux Kernel Configuration Device Drivers ---> <*> Industrial I/O support ---> Frequency Synthesizers DDS/PLL ---> Clock Generator/Distribution ---> <*> Analog Devices AD9528 Low Jitter Clock Generator
Channels can be specified using child nodes. The following properties are applicable to them:
The following example instanciates the ad9528 driver for a AD9528 device connected on the SPI bus to the chip-select line 0.
The various macros used are defined in the header file: <dt-bindings/iio/frequency/ad9528.h>
#include <dt-bindings/iio/frequency/ad9528.h> &fmc_spi { clk0_ad9528: ad9528@0 { #address-cells = <1>; #size-cells = <0>; #clock-cells = <1>; compatible = "ad9528"; spi-cpol; spi-cpha; spi-max-frequency = <1000000>; adi,spi-3wire-enable; reg = <0>; clock-output-names = "ad9528_out0", "ad9528_out1", "ad9528_out2", "ad9528_out3", "ad9528_out4", "ad9528_out5", "ad9528_out6", "ad9528_out7", "ad9528_out8", "ad9528_out9", "ad9528_out10", "ad9528_out11", "ad9528_out12", "ad9528_out13"; adi,vcxo-freq = <80000000>; /* PLL1 config */ adi,ref-mode = <REF_MODE_STAY_ON_REFB>; adi,refa-enable; adi,refa-diff-rcv-enable; adi,refa-r-div = <1>; adi,refb-r-div = <1>; adi,pll1-feedback-src-vcxo; adi,pll1-feedback-div = <8>; adi,osc-in-cmos-neg-inp-enable; adi,pll1-charge-pump-current-nA = <10000>; /* PLL2 config */ * Valid ranges based on VCO locking range: * 1150.000 MHz - 1341.666 MHz * 862.500 MHz - 1006.250 MHz * 690.000 MHz - 805.000 MHz */ adi,pll2-m1-frequency = <1000000000>; adi,pll2-charge-pump-current-nA = <805000>; /* SYSREF config */ adi,sysref-src = <SYSREF_SRC_INTERNAL>; adi,sysref-k-div = <20>; adi,rpole2 = <RPOLE2_900_OHM>; adi,rzero = <RZERO_3250_OHM>; adi,cpole1 = <CPOLE1_16_PF>; ad9528_0_c8: channel@8 { reg = <8>; adi,extended-name = "ADC1"; adi,driver-mode = <DRIVER_MODE_LVDS>; adi,divider-phase = <0>; adi,channel-divider = <1>; adi,signal-source = <SOURCE_VCO>; }; ad9528_0_c9: channel@9 { reg = <9>; adi,extended-name = "ADC1-sysref"; adi,driver-mode = <DRIVER_MODE_LVDS>; adi,divider-phase = <0>; adi,channel-divider = <1>; adi,signal-source = <SOURCE_SYSREF_VCO>; }; }; };