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resources:tools-software:crosscore:cces:getting-started:boot-app-sc5xx [27 Aug 2019 16:13] Steven MacDiarmidresources:tools-software:crosscore:cces:getting-started:boot-app-sc5xx [27 Aug 2019 16:14] (current) Steven MacDiarmid
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 //Figure 7: The loader file has been created// //Figure 7: The loader file has been created//
          
-11. Return to the [[resources:tools-software:crosscore:cces:getting-started:app|previous page]] to learn how to flash your loader file and application to your device.  +11. Return to the [[resources:tools-software:crosscore:cces:getting-started:app#Step 2: Write Application to Flash Memory|previous page]] to learn how to flash your loader file and application to your device.  
  
 //Aside:// When an application is loaded to a target using the debugger, the IDE can configure external memory as long as the processor is homogeneous (i.e. it has only SHARC cores). However, for heterogeneous processors, such as the ASDP-SC5xx series, which have an ARM core plus one or two SHARC cores,  a //preload file//, equivalent to an initialization file, is required. As with initialization files, pre-built preload files are located in the **<CCES Root>\SHARC\ldr\** directory, and CCES projects for customization can be found in **<CCES Root>\SHARC\ldr\init_code\SC57x_init\** directory. The master core is generally the only core that needs a preload file, so a new **Debug Configuration** session automatically includes the preload file as one of the applications that is to be loaded. For an ADSP-SC5xx processor, the preload file is included in the ARM© Core 0 project. More information about proper preload file configuration can be found in CCES Online Help under **CrossCore® Embedded Studio 2.9.0 → Integrated Development Environment → Debugging Targets → Debugging ADSP-SC5xx SHARC Targets → About Preload Files**. //Aside:// When an application is loaded to a target using the debugger, the IDE can configure external memory as long as the processor is homogeneous (i.e. it has only SHARC cores). However, for heterogeneous processors, such as the ASDP-SC5xx series, which have an ARM core plus one or two SHARC cores,  a //preload file//, equivalent to an initialization file, is required. As with initialization files, pre-built preload files are located in the **<CCES Root>\SHARC\ldr\** directory, and CCES projects for customization can be found in **<CCES Root>\SHARC\ldr\init_code\SC57x_init\** directory. The master core is generally the only core that needs a preload file, so a new **Debug Configuration** session automatically includes the preload file as one of the applications that is to be loaded. For an ADSP-SC5xx processor, the preload file is included in the ARM© Core 0 project. More information about proper preload file configuration can be found in CCES Online Help under **CrossCore® Embedded Studio 2.9.0 → Integrated Development Environment → Debugging Targets → Debugging ADSP-SC5xx SHARC Targets → About Preload Files**.
resources/tools-software/crosscore/cces/getting-started/boot-app-sc5xx.txt · Last modified: 27 Aug 2019 16:14 by Steven MacDiarmid