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This version (23 Jan 2013 18:07) was approved by Brandon.The Previously approved version (23 Jan 2013 13:33) is available.Diff

CN-0196 CSC Control Signal Converter

White Paper

The CN-0196-CSC is a Control Signal Circuit, to generate 2 signals 180 degree phase shifted, to provide a signal to the CFTL Evaluation board: EVAL-CN0196-EB1Z. CN-0196 As an input, a standard signal generator shall act as a source for the CSC. The symmetry of the CSC may not cause any long term DC offset drift on the AC output of the H-Bridge, to avoid magnetic biasing in inductive loads. Under any rectangular pulse pattern of the generator, the output drive may not cause a shortage of the H-Bridge supply. Focus is simplicity, so that the interface board can be self-made on a bread board with wire-wrapping. The components shall be available in DIL package (2.54mm raster) and passives with wires for thru hole mounting.

Setup without the CSC

The schematic of the CN-0196 (Fig.2) shows, that for the signal generation the EVAL-ADUC7061MKZ can be used. (The ADUC7061 is not part of the Circuit note) The purpose of using the ADUC7061 is, enabling and help designers to quickly implement a complete and integrated, microprocessor based signal generator. The source code of the ADUC7061 is part of the CN-0196 designer support package. The ADUC7061 is not part of the EVAL-CN0196-EB1Z. Analog Devices provides the GUI application support package. With some applications and experiments controlling the H-Bridge signal source with the PC GUI can be quite uncomfortable. The ADUC7061 evaluation board needs to be connected via an USB interface to the PC. The PC controls the parameters of the ADUC7061. So, for example: running the H-Bridge at 100kHz, and sweep +/-1kHz, smoothly, is not possible with the PC interface. The frequency change will be “jumpy”. An instant feedback via an Oscilloscope is delayed. Eventual resonant effects might be missed at very high Q-Factors. Similar scenario you will see when changing the pulse width. If you like to change the width in small fractions, you hit the limit of the capability of the setup as well. For cleanest clock source, a signal generator is the choice of preference in some cases. The Mini Evaluation board (Fig.1.), as it can be used as mentioned in the CN-0196

EVAL-ADUC7061MKZ

Fig. 1. EVAL-ADUC7061MKZ

CN-0196 Schematic

Fig. 2. Schematic of the CN-0196 Evaluation Platform (click to enlarge)

Technical Key-Specification of the CN-0186-EVALZ

As such data is missing in the actual circuit note, here a quick overview:

Subject of Specification Value Notes
Maximum useful operating frequency 1MHz You can go higher at increased losses
Smallest ON or OFF length 100ns See specification of ADUM7234, part of CN-0196
Maximum H-Bridge Voltage 24V with 1V margin. Electrolytic C. is the limit.
Maximum H-Bridge Current 80A MOSFET is the limiting factor
Max. Pulse Power output 1.92kW @24V, 80A
Max. Supply if El.Caps > 50V 50V Multilayer Ceramic Capacitors are the limit.

With proper MOSFETs (240A) and increased bridge supply voltage to 50V the pulse power can be increased up to 12kW peak. This is to tell a bit at which powerlevel we move with the technology at those conditions mentioned.

Basic Setup

With the CN-0196-CSC, you can use a single signal output laboratory style pulse generator with all its advantages. Laboratory type of signal generators can do automatic up/down sweep, random frequency generation, sequence of shots, external triggered, triggered with delay. Also PM and FM (Phase and Frequency Modulation) is a possible function with such equipment.

Some experiments might require using a VCO (Voltage Controlled Oscillator), or a PWM (Pulse Width Modulator) as signal generator. A VCO or PWM can be part of a feedback loop from the high power AC output of the MOSFET bridge.

In all those applications, a translation of a single line pulse train into a dual line pulse train with 180 degree phase shift is required. Otherwise we cannot produce the AC signal by the H-Bridge. Furthermore, the AC signal needs to be symmetric. Otherwise inductive systems with a magnetic core can run into DC saturation and becomes nonelinear.

Fig 3. Basic Setup

Fig. 3.

Fig.3 shows how a single pulse train (RED signal) is translated into a dual pulse train (“BLUE”, “GREEN” signal). Note, that the AC output frequency is always ½ the input frequency. The pulse Generator and the CN-0196-CSC replace the ADUC-7061MKZ. For applications and tests, where a pulse generator signal and the technical capability of the pulse generator is not sufficient, you might want to control the CN-0196-EVALZ by a DSP evaluation board. Such boards are available from Analog Devices as well. They are not part of this article. Blackfin processors can be used for 16 bit fixed point math, while the SHARC can be used for IEEE floating point math based algorithms. On the Analog Devices Motorcontrol site you may get even more components for building your Transistor driver system and control.

Schematic Description

The circuit in Fig. 4. has been tested in the National Instruments Spice Simulator: Multisim 12.0.1. V1 represents the signal source of a Generator. The signal from the generator shall be a square wave signal. Output swing from 0V … 5V. The signal source will also power the physical real circuit. Diode D1 charges thru R1, capacitor C1. (10µF). Diode D2 is just for protecting the logic gates against excessive over voltage in case of a real world misconfiguration of the generator. C1 is the power source for the 74HC logic. J1 connector represents the powersupply to the logic gate circuits.

CSC Schematic

Fig. 4.

Resistor R3 acts as a protection of the clock input of the HCMOS device. R2 builds the other part of electrical overstress protection in case you exceed 6V peak on the generator. Diode D3 (Shottky) protects against excessive negative voltage of the pulse generator in case of a misconfiguration. BAT43 is a Shottky diode with leads. In the schematic the Shottky diode my available only in SO package. You may use any Shottky diode in this application. U2A (74HC73) is a JK Flip-Flop. With every falling edge of signal from the generator, provided to the CLK pin 1, the output 1Q and ~1Q toggles. With the gate delay of U1A an U1B, both driver outputs (H1 and H2) go to low. The low duration time of any input pulse is the time, where none of the H-Bridge transistors are turned on.

Finally the AND gates U1A & U1B (74HC08) combine the JK-FF alternating outputs with the positive duration of the input clock.

Oscilloscope Pictures

All pictures shown here (so far), are simulated with NI Multisim 12.0.1. Fig 5. Shows the 74HC08 gate delay. Signal in red color is the clock input signal with 50ns long negative pulses. Blue and Green are the measured output signals . It demonstrates, that even at very small pulse length, the break before make criteria for the MOSFETs is met with 40ns gap. The pulse delay variation of the ADUM7234 has a channel to channel matching, rising vs. falling edges of 25ns. (see Datasheet of ADUM7234) The 40ns would be still a save timing. (considering also some rise vs. fall time differences of the MOSFETs). Before meeting those limits, it is recommended to verify with the actual hardware, at which pulse length you meet the 0ns margin.

Fig. 5.

Fig. 5. Small negative pulse length

Fig.6. shows close to the limit, what HCMOS logic can do. The pulse length of the input (red) is 50ns. At 1µs period (1MHz), the blue and red output signals follow in an alternating way as expected. It results in a 500kHz output control signal. The H-Bridge would switch at 500kHz, with 50ns on-time per half-period.

Fig. 6.

Fig. 6. 50ns high time pulses.

Fig.7. shows the delayed output of the 50ns input pulse. For very short pulses you can go as close as the 74HC gates allow. However, 100ns pulse length is the shortest time the ADUM7234 datasheet specifies, where all the timing parameters are guaranteed. For test-purpose you might go below 100ns, while observing the output of the H-Bridge on a resistive load.

Fig. 7. 20ns positive pulse length

Summary

2 HCMOS logic gate ICs with a few passives turns your signal generator in a special H-Bridge driver lab equipment. So far no PCB ready made exists. The hardware is easy to do yourself. The circuit does not need an external powersupply as the HCMOS logic consumes little enough energy to be supplied by the signal generator. At periodic signals, the output signal for driving the H-Bridge are absolutely symmetric. It is guaranteed by the nature of the JK-FF. This provides an AC Signal to inductive loads without DC biasing. The HCMOS logic covers clocking speed beyond what usually is needet.

FILES for Download

Schematic as PDF: CN-0196-CSC-SCH

Multisim 12.0 (for Power Pro Edition), BOM and NETLIST: Multisim 12.0 File (Note: The free Analog Devices Comoponent Evaluator from NI (which is a free Multisim version with restrictions) does not allow to load this file. The quickest way for those who like to simulate the schematic is, to re-enter the schematic in the component evaluator. (nice exercise btw.)

Technical Key-Specification of the CN-0196-EVALZ

As such data is missing in the actual circuit note, here a quick overview:

Subject of Specification Value Notes
Maximum useful operating frequency 1MHz You can go higher at increased losses
Smallest ON or OFF length 100ns See specification of ADUM7234, part of CN-0196
Maximum H-Bridge Voltage 24V with 1V margin. Electrolytic C. is the limit.
Maximum H-Bridge Current 80A MOSFET is the limiting factor
Max. Pulse Power output 1.92kW @24V, 80A
Max. Supply if El.Caps > 50V 50V Multilayer Ceramic Capacitors are the limit.

With proper MOSFETs (240A) and increased bridge supply voltage to 50V the pulse power can be increased up to 12kW peak. This is to tell a bit at which powerlevel we move with the technology at those conditions mentioned.

resources/technical-guides/cn-0196-csc.txt · Last modified: 23 Jan 2013 18:07 by Brandon

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