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resources:quick-start:ad5791 [10 Apr 2013 21:03] – table formatting Yuet Ng | resources:quick-start:ad5791 [16 Apr 2013 16:18] (current) – text edits throughout Yuet Ng | ||
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====== AD5781/ | ====== AD5781/ | ||
** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface ** | ** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface ** | ||
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- | {{ : | ||
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- | <WRAP CENTERALIGN>// | ||
- | <WRAP clear></ | ||
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===== Features ===== | ===== Features ===== | ||
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* High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi> | * High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi> | ||
* 1 ppm resolution, 1 ppm INL (20-bit [[adi> | * 1 ppm resolution, 1 ppm INL (20-bit [[adi> | ||
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* 35 MHz Schmitt triggered digital interface | * 35 MHz Schmitt triggered digital interface | ||
* 1.8 V compatible digital interface | * 1.8 V compatible digital interface | ||
+ | |||
+ | ===== Functional Block Diagram ===== | ||
+ | {{ : | ||
+ | <WRAP CENTERALIGN>// | ||
+ | <WRAP clear></ | ||
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===== Pin Configuration ===== | ===== Pin Configuration ===== | ||
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<WRAP CENTERALIGN> | <WRAP CENTERALIGN> | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
<WRAP clear></ | <WRAP clear></ | ||
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^/ | ^/ | ||
|X< | |X< | ||
- | |X< | + | |X< |
|0 |0 | |0 |0 | ||
|0 |1 | |0 |1 | ||
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
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|:::|0 (default) | |:::|0 (default) | ||
|::: | |::: | ||
- | |LIN COMP |Linearity error compensation for varying reference input spans. || | + | |LIN COMP |Linearity error compensation for varying reference input spans. Note that the reference input span options for the [[adi> |
|::: | |::: | ||
|:::|0000 (default) | |:::|0000 (default) | ||
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
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**Table 5. Software Control Register Functions** | **Table 5. Software Control Register Functions** | ||
- | ^Bit Name ^Description^ | + | ^Bit Name ^Description |
- | |LDAC< | + | |LDAC< |
|CLR< | |CLR< | ||
|RESET | |RESET | ||
- | \\ | + | < |
- | < | + | < |
- | < | + | |
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To initialize the part, | To initialize the part, | ||
- | | + | |
- | - Because this initialization is a write to the part, set the R/W bit to a Logic 0. | + | |
- | | + | * To write in binary coding, select BIN/2sC = 1. |
- | | + | |
- | See Table 6. | + | Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/< |
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- | Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/< | + | See Table 6 and Figure 6. |
- | + | \\ | |
- | </ | + | |
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**Table 6. Bit Settings to Initialize and Write to the Part** | **Table 6. Bit Settings to Initialize and Write to the Part** | ||
- | ^Bit(s) | + | ^Bit(s) |
- | |[3: | + | |23 |R/< |
- | |23 |R/< | + | |[22: |
- | |4 |BIN/ | + | |[9:6] |LIN COMP |0000 |Linearity error compensation for a reference input span up to 10 V | |
- | |1 |RBUF | + | |
|5 |SDODIS | |5 |SDODIS | ||
- | |[9:6] |LIN COMP |0000 |Linearity error compensation for a reference input span up to 10 V. | | + | |4 |BIN/ |
- | \\ | + | |3 |DACTRI |
+ | |2 |OPGND | ||
+ | |1 |RBUF | 1 |Internal amplifier powered down | | ||
- | <WRAP important> | + | < |
- | To write in binary coding | + | To write in offset |
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The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading | The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading | ||
</ | </ | ||
+ | </ | ||
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+ | |||
{{ : | {{ : | ||
<WRAP CENTERALIGN>// | <WRAP CENTERALIGN>// | ||
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=== Writing to the DAC Register === | === Writing to the DAC Register === | ||
- | <WRAP tip>To write a midscale code to the DAC register, select the write option from the read/write bit (**R/W = "0" | + | <WRAP tip>To write a midscale code to the DAC register, |
- | \\ | + | * Set R/< |
- | \\ | + | |
- | The 24-bit data to write over the serial interface is: | + | |
+ | The 24-bit data to write over the serial interface is as follows: | ||
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20-bit [[adi> | 20-bit [[adi> | ||
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+ | \\ | ||
+ | where X = don't care. | ||
+ | \\ | ||
+ | \\ | ||
+ | See Table 7 and Figure 7. | ||
+ | \\ | ||
+ | \\ | ||
+ | **Table 7. Bit Settings to Write to DAC Register** | ||
+ | ^Bit(s) | ||
+ | |23 |R/< | ||
+ | |[22: | ||
</ | </ | ||
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
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- | ===== Example 2: Clear the DAC to a defined value ===== | + | ===== Example 2: Clearing |
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=== Writing to the Clearcode Register === | === Writing to the Clearcode Register === | ||
- | <WRAP tip>To define the value at which the DAC output is set when the CLR pin or CLR bit in the software control register is asserted, write the desired code to the clearcode register. | + | <WRAP tip>To define the value at which the DAC output is set when the < |
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- | For a full scale clear code, write the following over the serial interface: | + | For a full-scale clear code, write the following over the serial interface: |
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- | 18-bit | + | 18-bit |
+ | \\ | ||
+ | 20-bit [[adi> | ||
+ | \\ | ||
+ | \\ | ||
+ | where X = don't care. | ||
+ | \\ | ||
+ | \\ | ||
+ | See Figure 8. | ||
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- | 20-bit **AD5791**: 0011 1111 1111 1111 1111 1111 | ||
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</ | </ | ||
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
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- | === Writting | + | === Writing |
- | <WRAP tip>To set the DAC register to a user defined value and update the DAC output | + | <WRAP tip>Set the CLR bit to a Logic 1 to set the DAC register to a user defined value and update the DAC output. |
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- | The user should see the DAC output value change to full scale code. | + | The user should see the DAC output value change to full-scale code. |
+ | \\ | ||
+ | \\ | ||
+ | See Figure 9. | ||
</ | </ | ||
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
+ | \\ | ||
+ | \\ | ||
+ | === Reading From the Clearcode Register === | ||
+ | <WRAP tip>To confirm the clearcode value written to the part, read the data from the clearcode register (full scale for this example). | ||
+ | \\ | ||
+ | \\ | ||
+ | Write the following over the serial interface: | ||
+ | \\ | ||
+ | \\ | ||
+ | 1011 XXXX XXXX XXXX XXXX XXXX | ||
+ | \\ | ||
+ | \\ | ||
+ | where X = don't care. | ||
+ | \\ | ||
+ | \\ | ||
+ | See Figure 10. | ||
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- | === Readback the Clearcode Register === | ||
- | <WRAP tip>To confirm the clearcode value written to the part, read the data on the clearcode register (Full scale for this example). Write the following over the serial interface: 1011 XXXX XXXX XXXX XXXX XXXX. | ||
<WRAP center round important 60%> | <WRAP center round important 60%> | ||
- | Remember | + | Note that this action is a read function. Therefore, set the R/< |
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- | The data bits are **don't care**, as the aim is to read from the part and not a write function. | + | D19 to D0, the data bits, are don't care bits because |
</ | </ | ||
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{{ : | {{ : | ||
- | <WRAP CENTERALIGN>// | + | <WRAP CENTERALIGN>// |
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